Multi$-$Cycle Arch. Given the following code. Assume that $x$ and $y$ are arrays of words and the base address of $x$ is stored in $R1$ and the base address of $y$ is stored in $R2.$ Assume that each add operation takes $4$ cycles to execute, each $lw$ operation $5$ cycles, each store sw takes $4$ cycles, and each branch $($bne$)$ instruction takes $3$ cycles to execute. The $"T"$ represents Temp registers. All numbers are in decimal

$?$hat is the PC value for the SW instruction.

$200$

$135$

$120$

$124$