Multisim Please

You are required to use half adders, full adders and AND gates to implement this multiplier.

Design: draw out the logic diagram of the multiplier (e.g. see the logic diagram of a 2-bit and 2-bit multiplier illustrated in the Pre-lab and Background Information). Remember, you may only use half adders, full adders and AND gates. You will need to include this logic diagram in your lab report.

Create a new design file In this design file, draw the circuit you have designed from step 1. You may use SPDT switches to provide the multiplicand and multiplier inputs. You may also use LED arrays to demonstrate your resulting binary number of the multiplier (each LED can be used for a single bit in the multiplier result).

Run simulations to test your design. You should test a few possible pairs of the numbers A and B, e.g. multiply the decimal equivalents: 8x2, 11x3, etc. You should verify that the results generated (as indicated in the LED lights if you choose to use the LED lights to demonstrate your multiplication results) are correct for each of the number pairs. Capture a screenshot for each of the A & B number pairs you tested and include an explanation on how you can conclude that your circuit is functioning correctly.

Once you have verified your design logically in step 3, use your multiplier to conduct the following multiplications, use a table to list your inputs and expected outputs. Capture a screen shot for each of the following multiplications and include an explanation on how you verify that your circuit does the multiplications correctly for the following cases.

5x3

15x5

9x7

15x7

In the part of the lab, you are required to design a multiplier, which does the multiplication of a 3-bit number B(2:0) by a 4-bit number A(3:0) The multiplication process can be illustrated as follows: Adder A3 A2 A1 A0 Mutiplicand AND gate BOA3 BOA2 BOA1 BOAO B1A3 B1A2 B1A1: B1A0 Partial Products + B2A3 B2A2 B2A1 B2AO C6 C5 C4 C3 C2 C1 CO Results In the part of the lab, you are required to design a multiplier, which does the multiplication of a 3-bit number B(2:0) by a 4-bit number A(3:0) The multiplication process can be illustrated as follows: Adder A3 A2 A1 A0 Mutiplicand AND gate BOA3 BOA2 BOA1 BOAO B1A3 B1A2 B1A1: B1A0 Partial Products + B2A3 B2A2 B2A1 B2AO C6 C5 C4 C3 C2 C1 CO Results