NEED ASAP WILL RATE RIGHT AWAY!

1. Examine the Verilog HDL model of the clock_en module that is shown below. . module clock e (en out16,en out., clk) inpat clk ouzput reg en outl6, en out: reg tB:01 count.1: rea [3:01 count2: always (posedge clk) begin en out0: en out16-0 it (count1--325 begin en out16-1: counti -0: it (count2--15 begin on out-1: count2 -0 end else begin count2-count2 +1 end end begin end else counti-counti + 1 end endmodnle Why do you think the countl and count2 register values have the array dimensions they have been assigned in the reg declaration? If the clk input is driven exactly at 50 Mhz calculate the actual frequency of the en out16 sig- nal. How much does it differ from the targeted 16x9600 frequency? 1. Examine the Verilog HDL model of the clock_en module that is shown below. . module clock e (en out16,en out., clk) inpat clk ouzput reg en outl6, en out: reg tB:01 count.1: rea [3:01 count2: always (posedge clk) begin en out0: en out16-0 it (count1--325 begin en out16-1: counti -0: it (count2--15 begin on out-1: count2 -0 end else begin count2-count2 +1 end end begin end else counti-counti + 1 end endmodnle Why do you think the countl and count2 register values have the array dimensions they have been assigned in the reg declaration? If the clk input is driven exactly at 50 Mhz calculate the actual frequency of the en out16 sig- nal. How much does it differ from the targeted 16x9600 frequency