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w Question#2: The following VHDL code implements LIBRARY ieee a finite state machine (FSM). Answer the following USE ieee std.logic.1164all questions: ENTITY prob8.4 IS A. Write down the state table of the system. PORT (Clock N STD.LOGIC B. Draw the state diagram of the system. Resetn IN STD.LOGIC C. Calculate the output 'z' if the input sequence IN STD.LOGIC OUT STD.LOGIC): 'w' is "010111100110011111"; END prob8.4 ARCHITECTURE Behavior of prob8.4 IS TYPE State_type IS (A, BC, D, E, F): SIGNAL Y State_type BEGIN PROCESS (Resetn, Clock) BEGIN IF Resetn = '0THEN y IF = 0 THEN y IFw='0THEN Y IFW-'0' THEN Y IFw='0' THEN y IFw='0' THEN Y IFw='0' THEN Y IF = 0 THEN y IFw='0THEN Y IFW-'0' THEN Y IFw='0' THEN y IFw='0' THEN Y IFw='0' THEN Y