Need these screenshots

1. Code screenshot of arrmul.sv file and upload the file separately. 2. [1 points] Screenshot of successful compilation of arrmul module. 3. [3 points] Screenshot of simulation result for the module. 4. [1 points] Screenshot of RTL Viewer of the module.

Code: might need additions

/* ECE 37100 Lab 2 Array multiplier for unsigned 4-bit inputs Input: X 4-bit, Y 4-bit Output: P 8-bit */

module halfadd(input logic a, b, output logic s, c); // Write your code endmodule

module fulladd(input logic a, b, cin, output logic s, cout); // Write your code endmodule

module arrmul(input logic[3:0] X, input logic[3:0] Y, output logic[7:0] P); logic X3Y0, X2Y0, X1Y0, X0Y0; logic X3Y1, X2Y1, X1Y1, X0Y1; logic X3Y2, X2Y2, X1Y2, X0Y2; logic X3Y3, X2Y3, X1Y3, X0Y3; logic S10, S11, S12, S13; logic C10, C11, C12, C13; logic S20, S21, S22, S23; logic C20, C21, C22, C23; logic S30, S31, S32, S33; logic C30, C31, C32, C33; assign X0Y0 = X[0] & Y[0]; assign P[0] = X0Y0; // Write your code for P[1] - P[6] assign P[7] = C33; endmodule

Use the arrmul.sv file as a template to implement a 4x4-array multiplier module arrmul. Perform the following activities to complete the task: 1. Create a new Quartus Prime project using File -> New -> New Quartus Prime Project with the following attributes: a. Project Directory: lab3 b. Project Name: lab3 c. Top-level Entity: arrmul 2. Add the template file arrmul.sv in the project using Project -> Add/Remove files in project. Browse the arrmul.sv file and add it into the project. Set this file as top-level entity. 3. Complete the arrmul.sv file. 4. Perform Analysis & Synthesis using Processing -> Start -> Analysis & Synthesis. 5. The compilation should take place without errors and warnings. If you find any error or warnings, then fix it. 6. Create a University Program VWF using File -> New -> University Program VWF. Configure the file with the following specification: a. Insert all signal nodes/buses using Edit -> Insert -> Insert Node or Bus -> Node Finder -> List. Then add all the nodes in Nodes found to Selected Nodes by pressing the >> button. b. Set the simulation end time to 10ns using Edit -> Set End Time. c. Set the grid size to 1ns using Edit -> Grid Size. d. Use the Random values button to configure input signals to cycle through random logic bus values throughout the simulation. e. Start functional simulation using Simulation -> Run Functional Simulation and verify whether outputs are getting the correct values.

Objectives Able to use structural modeling to implement complex circuits. Able to use always_comb, case, and if-else statements in SystemVerilog. Able to write a testbench for simulation. Tasks Task 1 [10 points]. An array multiplier is a parallel multiplier that generates the partial products in a parallel fashion. The various products are added as soon as they are available. Two N-bit unsigned numbers X and Y are multiplied to generate a product that is possibly 2N bits. Figure 1 shows two 4-bit unsigned numbers X and Y multiplication. In general, an N- bit multiplier would require N2 AND gates, N*(N-2) full adder, and N half-adder.

(Figure 1 here) .

Half adder: A half adder has two inputs, A and B, and two outputs, S and Cout. S is the sum of A and B. Cout holds the carry out of the sum. The half adder can be built from an XOR gate and an AND gate. SCout=AB=AB Figure 2: Half adder Full adder: A full adder has three inputs, A, B, and Cin along with two outputs, S and Cout. S is the sum of A,B, and Cin. Cout holds the carry out of the sum. SCout=ABCin=AB+ACin+BCin Figure 1: 4-bit array multiplier