Need to to revise the VHDL code for MIPS to generate the appropriate control signal (ALUctl(3:0)) based on the 6-bit function code or the last 6 bit of instruction word (instruction_mips(5:0))

Below is the MIPS code that needs to be modified:

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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mips is port (clock_mips : in std_logic; reset_mips : in std_logic; memory_in_mips : out std_logic_vector (31 downto 0); -- data to write into memory (sw) memory_out_mips : in std_logic_vector (31 downto 0); -- data being read from memory (lw) memory_address_mips : out std_logic_vector (31 downto 0); -- memory address to read/write pc_mips : out std_logic_vector (31 downto 0); -- instruction address to fetch instruction_mips : in std_logic_vector (31 downto 0); -- instruction data to execute in the next cycle overflow_mips : out std_logic_vector (3 downto 0); -- flag for overflow memory_write_mips : out std_logic); -- control signal for data memory read/write end entity; architecture rtl of mips is ------ Signal Declaration ------ signal X : std_logic_vector (31 downto 0); -- instruction address to fetch signal Y : std_logic_vector (31 downto 0); -- memory address to read/write signal A, B : std_logic_vector (31 downto 0); -- ALU input values signal ALUOut : std_logic_vector (31 downto 0); -- ALU output value signal ALUctl : std_logic_vector (3 downto 0); -- ALU output value signal overflow : std_logic; -- overflow flag signal Zero : std_logic; -- 1 bit signals for ALU arithmetic operations ------ Project 1 Signals (your code) ------ -- signal ????? ------ Component Declarations ------ component ALU_32 port( A_alu32 : in std_logic_vector(31 downto 0); -- A input B_alu32 : in std_logic_vector(31 downto 0); -- B input ALUctl_alu32 : in std_logic_vector(3 downto 0); -- control ALUout_alu32 : out std_logic_vector(31 downto 0); -- result overflow_alu32: out std_logic; -- overflow result Zero_alu32 : out std_logic); -- check if ALUout is zero end component ; begin ------ Component Instantiations ------ ALU_32_1 : ALU_32 port map ( A_alu32 => A, B_alu32 => B, ALUctl_alu32 => ALUctl, ALUout_alu32=>ALUout, overflow_alu32=>overflow, Zero_alu32=>Zero); ------ Project 1 Signal Mapping (your code) ------ ALUctl