Need VHDL code for this question with same entity.

Introduction You are part of the senior design team that has been allocated a task to design a simple 8-bit ALU (Arithmetic Logic Unit). ALU is the workshop of the CPU, it carries out all the calculations, and this includes the logical operations which are applied to either the contents of the data register or the Memory Buffer Register (MBR). ALUs operations involve operations such as shift, carry, add, subtract, rotate etc. The following entity declaration is provided. Your design must adapt to the Entity below. library IEEE; use IEEE.std_logic_1164.all; entity ALU is port (A,B : in std_logic_vector(7 downto 0); Op : in std_logic_vector (3 downto 0); cout : out std_logic; Equal : out std_logic); end; The Equal output is ' 1 ' if and only A=B, otherwise ' 0 ' . The block diagram of an ALU is shown in figure 1.1. Note that all A and B operands are type std_logic_vector. All the arithmetic operations are evaluated using the type signed. Port Op (Op-code) is type std_log ic_vector. Sixteen binary codes indicate 13 different operations and 3 unused operations. The Same binary codes are to be used for operations when the ALU is synthesized. The outputs can be any logic value for unused operations but be careful not to synthesize transparent latches. The following table shows the detailed operation of an ALU. Table 1 ALU operation The shift operations are logical shifts, shifting one place left or right and setting the vacated bit to zero. Shift left and move bit 7 into Cout. Rotate left and move bit 7 to both bit 0 and to Cout. Rotate right move bit 0 to bit 7 (see the ALU table 1.1 above). For all the operations except shift and rotate, the inputs A and B are interpreted as signed 2's Complement 8-bit numbers, and the result is signed 9-bit numbers. The lower 8-bit of the result are to F, and the 9th bit of the result is assigned to Cout. Which is effectively the signed