New Program to be done:

Extend Pgm3 to include the Control and ALU Control modules (from Figure 4.24 in the Pgm3 assignment) which are then tested in the testbench to verify that the appropriate signal values are generated for the list of supported instructions. The file pgm4text.hex has all of the supported instructions included in hexadecimal machine code format. In addition to displaying the instruction as was done in Pgm3, display the associated control signals for each instruction.

Submit code, report, and test output here.

Program code for pgm3:

module Clock(output clock); parameter HI=10, LO=10; reg clock; initial clock = 0;

always begin #HI clock = ~clock; #LO clock = ~clock; end endmodule

module Adder(output [31:0] S, input [31:0] A, input [31:0] B); assign S = A + B; endmodule

module PC(output [31:0] oldAddress, input [31:0] newAddress, input clock); reg [31:0] address; always @(posedge clock) address = newAddress; assign oldAddress = address; endmodule

module InstructionMemory(output [31:0] instruction, input [31:0] address); reg [31:0] mem [0:12'h7FF]; assign instruction = mem[address >> 2]; endmodule

module testbench; wire [31:0] newAddress, oldAddress, instruction; wire clock; reg [11:0] ix; Clock c(clock); PC pc(oldAddress, newAddress, clock); InstructionMemory im(instruction, oldAddress); Adder add(newAddress, oldAddress, 32'd4); initial begin pc.address = 32'h00000000; ix = 0; repeat (2048) im.mem[ix++] = 0; $readmemh(\"text.hex\", im.mem); end // Everything past this point was written by me, class ended before he could finish going over the testbench always @(posedge clock) begin if (instruction == 32'h00000000) $finish; $display(\"Instruction = %h\", instruction); casex (instruction[31:26]) 6'b000000: $display(\"opcode=%b => R-Type \", instruction[31:26]); 6'b00001X: $display(\"opcode=%b => J-Type \", instruction[31:26]); default: $display(\"opcode=%b => I-Type \", instruction[31:26]); endcase end endmodule

pgm4text.hex:

supported.txt: