o) Write a SystemVerilog model of an 3216-bit register file, with the following features: - A positive edge-triggered clock; - A 16-bit write data input; - Two 16-bit read data outputs; - Two 4-bit address inputs; - A one bit write control input; - If the write control input is 1 , the register is loaded on the positive edge of the clock with the data from the write data input to the register at the address given by the second address input; - If the write control input is 0 , the contents of the register at the addresses given by the two address inputs are directed to the two data outputs; - Reading from address 0 should always give all zeros at the output. If your model were synthesised to a modern FPGA, what resources would you expect to see used? [15 marks] c) Write a SystemVerilog testbench for this model. Your testbench should verify that the model can store and write data