Objectives

Use a VHDL signal to describe an internal node

Implement a PLA-style digital circuit to control a 7-segment display digit

Verify correct operation using perfect induction (exhaustive testing) on the board

Functional Specification

In this lab you will implement and test a circuit that displays a hexadecimal digit that corresponds to the binary number entered using four switches. 1. I/O a. Switches SW3, SW2, SW1 and SW0, inputs, STD_LOGIC b. 7-segment display SEGMENT_A, SEGMENT_B, ..., SEGMENT_G, outputs, STD_LOGIC c. 7-segment display ANODE3, ANODE2, ANODE1, ANODE0, outputs, STD_LOGIC 2.

Operation

a. The rightmost digit of the 7-segment display shows the hexadecimal digit corresponding to the binary number entered using the switches.

b. The other three digits are blank (off).

This is my code thus far. Can you show me the correct VHDL code for this?

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-------------------------------------------------------------------------------- entity Lab04_xxxxxx is port ( SW3 : in STD_LOGIC; SW2 : in STD_LOGIC; SW1 : in STD_LOGIC; SW0 : in STD_LOGIC; SEGMENT_A : out STD_LOGIC; SEGMENT_B : out STD_LOGIC; SEGMENT_C : out STD_LOGIC; SEGMENT_D : out STD_LOGIC; SEGMENT_E : out STD_LOGIC; SEGMENT_F : out STD_LOGIC; SEGMENT_G : out STD_LOGIC; ANODE0 : out STD_LOGIC; ANODE1 : out STD_LOGIC; ANODE2 : out STD_LOGIC; ANODE3 : out STD_LOGIC ); end entity; --------------------------------------------------------------------------------

architecture Structural of Lab04_xxxxxx is

-- Input aliases alias A : STD_LOGIC is SW3; alias B : STD_LOGIC is SW2; alias C : STD_LOGIC is SW1; alias D : STD_LOGIC is SW0;

-- Output aliases alias Y1 : STD_LOGIC is SEGMENT_A; alias Y2 : STD_LOGIC is SEGMENT_B; alias Y3 : STD_LOGIC is SEGMENT_C; alias Y4 : STD_LOGIC is SEGMENT_D; alias Y5 : STD_LOGIC is SEGMENT_E; alias Y6 : STD_LOGIC is SEGMENT_F; alias Y7 : STD_LOGIC is SEGMENT_G; -- Internal signals (minterms) signal m0 : STD_LOGIC; signal m1 : STD_LOGIC; signal m2 : STD_LOGIC; signal m3 : STD_LOGIC; signal m4 : STD_LOGIC; signal m5 : STD_LOGIC; signal m6 : STD_LOGIC; signal m7 : STD_LOGIC; signal m8 : STD_LOGIC; signal m9 : STD_LOGIC; signal m10 : STD_LOGIC; signal m11 : STD_LOGIC; signal m12 : STD_LOGIC; signal m13 : STD_LOGIC; signal m14 : STD_LOGIC; signal m15 : STD_LOGIC; begin

m0 SMS