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OE 3 0 2 0 1 T 2 3 2 Assignment # 3 Design and Implementation of a Quadratic Equation Solver in Verilog Objective: Your
OE T
Assignment #
Design and Implementation of a Quadratic Equation Solver in Verilog
Objective:
Your task is to model a digital circuit using Verilog that solves quadratic equations. This circuit should be
capable of handling signed fixedpoint numbers for its calculations. You will apply your knowledge of Verilog
coding and digital circuit design to create an efficient and accurate solver that adheres to the specifications
outlined below.
Parameters:
WIDTH: Specifies the width in bits of the fixedpoint numbers used in this assignment.
SCALE: Specifies the number of bits used for the fractional part in the fixedpoint representation.
Note: All fixedpoint numbers used for this assignment must be signed.
Inputs:
reset: Resets the circuit to the initial state.
go: This input signal is used to initiate the reading of equation coefficients, a b and c
din: A WIDTHbit data input port through which the coefficients a b and c are sequentially read.
Outputs:
rdy: An output signal that indicates when the output solution to the equation is ready to be consumed.
dout: A WIDTHbit data output port that serially outputs the solutions real and imaginary parts over
four consecutive clock cycles.
Algorithm:
rdy
wait for ve edge on go
a din; rdy ;
wait for ve edge on go
b din
wait for ve edge on go
c din
D bb ac
if D simplest case Repeated real root
xr ba; xi ;
xr ba; xi ;
else if D Two distinct real roots
s sqrtD; done in a separate clock cycle than the assignments below it
xr bsa; xi ;
xr bsa; xi ;
else
s sqrtD; done in a separate clock cycle than the assignments below it
xr ba; xi sa;
xr ba; xi sa;
end if
rdy ; dout xr;
dout xi;
dout xr;
dout xi; goto
Deliverables:
As part of your submission for the Quadratic Equation Sol
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