On the vertical axis is the number of cycles for one memory read instruction. The horizontal axis is the size

of the test array in bytes.

How many levels of caching is used by computer A and how large are these caches?

How many levels of caching is used by computer $B$ and how large are these caches?B$.$ Now consider the following two implementations of a horizontal flip and copy of the matrix. Again

assume that the src matrix starts at address $0$ and that the dest matrix follows immediately follows it$.$

void copy$\_$n$\_$flip$\_$matrix$1($int dest$[$ROWS$][$COLS$],$ int src$[$ROWS$][$COLS$])$

$\{$

int i$,$ j;

for ROWS; $i++$

for COLS ;$j++$

dest$[i][COLS-1-j]=src[i][j]$;

$\}$

$\}$

$\}$

What is the cache miss rate if ROWS $=128$ and COLS $=128?$

Miss rate $=$

$\%$

What is the cache miss rate if ROWS $=128$ and COLS $=192?$

Miss rate $=$

$\%$

void copy$\_$n$\_$flip$\_$matrix$2($int dest$[$ROWS$][$COLS$],$ int src$[$ROWS$][$COLS$])$

$\{$

int i$,$ j;

for COLS ;$j++$

for ROWS; $i++$

dest$[i][COLS-1-j]=src[i][j]$;

$\}$

$\}$

$\}$

What is the cache miss rate if ROWS $=128$ and COLS $=128?$

Miss rate $=$

$\%$

What is the cache miss rate if ROWS $=192$ and COLS $=128?$

Miss rate $=$Problem $5.(8$ points$)$:

A$.$ You are given the following loop:

for

prod$=$prod$**vec[i]$;

$\}$

That compiles into the following assembly code:

mov$1$ $$0$x$1,\%$eax

mov$1$ $$0$x$0,\%$esi

$.$ L$2$ :

imul Oxfffffde$8(\%$ebp, $\%$esi, $4),\%$eax

inc$1\%$esi

cmp$1$ $$0$x$80,\%$esi

j$1.$ L$2$

Calculate the CPE $($cycles per element$)$ of this loop assuming $4$ cycles for a multiply instruction, $3$

cycles for a memory load, and $1$ cycle for all other instructions. The processor is fully pipelined, and

can issue multiple instructions every cycle. For simplicity, assume there is an unbounded number of

functional units. Also assume that the processor makes no branch mispredictions.