One application of a MOS capacitor is as a Varactor, a variable capacitance element tunable with voltage. To get a good varactor we want to maximize the ratio of the maximum capacitance to the minimum capacitance. Assuming you can choose SiO2 thickness (but no less than 100nm) and Si doping (but no less than 1014), design a Si MOS varactor with Cmax/Cmin = 3? Is it possible to get Cmax/Cmin = 10? Provide an example OR show that it's not possible. Assume you are looking for steady state capacitance (so no Deep Depletion allowed)