Out of 1000 instructions fetched, 900 hit in the I-Cache, 40% are load-store instructions, 300 hit in the D- Cache, What are the I-cache and D-cache miss rates? * Consider the following code sequence lw $3, 0(S5) lw $4, 4(S5) add S7, $7, $3 add $8, $8, $4 add $10, $7, $8 sw $6, 0($5) Assume that a register read and register write in the same clock cycle is possible a. Without any forwarding hardware in the pipelined datapath, how many cycles does this code sequence take to execute? b. With forwarding hardware in the pipelined datapath, how many cycles does it take to execute? c. With forwarding hardware in the pipelined datapath, reorder the instruction so that it takes the minimum nmber of clock cycles