Page 14 Question 2: [18 marks] (a) What is meant by read after write register file? Why is it used? [3 marks] (b) For the pipeline computer execution pattern shown in figure Q2(b2), the sequence of the five instructions in the following program are fetched and executed, (first column gives the address of the memory location). Assume the clock frequency of 1.2GHz. (all values are in hexadecimal) 200 201 202 203 204 LDI LDI OR MOVA ADD R3,4 R4,3 R6, R3, R4 R5, R3 R7, R3, R4 O How many clock cycles are required to execute the program? [3 marks] (ii) What is the time required to execute the program? [3 marks] (iii) Manually simulate the execution of the program by giving the values in the pipeline registers PC, IR, Data A, Data B, Data F, Data I and the register file (only when a change in value occurs) for each clock cycle. Assume that all file registers initially contain -1 (i.e. all bitts are 1s). (use Figure Q2(b1)). (9 marks) 15 98 63 32 O Destination Opcode Source reg. ister A (SA) Source rep register (DR) ister B (SB) (a) Register 15 98 63 Opcode Source res Destination register (DR) ister A (SA) Operand (OP) (bi Immediate 15 98 65 Address IAD (Left) 32 D Source res: Address LAD ister A (SA) (Right) Opcode (e) Jump and Branch Figure Q2(61) PC 11 Stage Address Instruction memory Instruction IK DOS Register bic AAA dute B data-BA Zero full Stage Instruction decoder MUXBMB AA BAMB 1 DOR Data A Data B 7 FS Address out MW B FS Address Stage Function V tinit Data memory Z Dala Data in Date out Datat Dete in Address MW EN w DaF MD RW Stage DA MDMUX D Date memory semes above RW DA- CONTROL DATAPATH D dat Register fisie 10thos) Figure Q2(62)