Parallel load 4) Traffic lights are installed on an intersection of a busy highway and a local farm road. A single car detector is installed on farm road, asserting signal Car high in the presence of a car on the farm road approaching the intersection. In the initial state, the highway (H) lights must be Green and the farm-road (F) light must be Red. As soon a car is detected on the farm road approaching the intersection, the highway lights should cycle from Green (G) through Yellow (Y) to Red (R), and the farm road light should subsequently turn Green. Each of those transitions should take one clock cycle. The farm road lights are to remain Green for as long as signal Car remains high (1). As soon as signal Car turns low (0), the farm road lights should cycle through Yellow to Red, and then the highway lights should turn Green. Each of those transitions should also take one clock cycle. Note: When the light on one road is green or yellow, the light on the other road must be red. INPUTS: Your Traffic Light Controller (TLC) circuit has one primary input, a sensor, Car, and a periodic clock signal, Cik. OUTPUTS: The circuit should have six traffic light outputs: three for the highway lights (HG, HY, HR) and three for the farm road lights (FG, FY, FR). These signals can be derived directly from the state registers. INITIAL STATE of your circuit is Sq=HG/FR, i.e. Highway green and Farm road red. Synthesize the TLC circuit as a Moore FSM by performing the following tasks: a) Derive and draw the state diagram for your design, using as few states as possible. Use the names used above to create meaningful names for the states, e.g., Sq=HG/FR, etc. b) Encode the states and convert your state diagram to a state transition table. c) Derive the final implementation with a minimum number of logic gates and show the resulting gate-level schematic (you can use any type of logic gates as needed). d) Using the minimized logic solution from item 3 above, implement the circuit as a PLA. Clearly show the content of the PLA and how its inputs and outputs are connected to the state registers to form the sequential machine. Parallel load 4) Traffic lights are installed on an intersection of a busy highway and a local farm road. A single car detector is installed on farm road, asserting signal Car high in the presence of a car on the farm road approaching the intersection. In the initial state, the highway (H) lights must be Green and the farm-road (F) light must be Red. As soon a car is detected on the farm road approaching the intersection, the highway lights should cycle from Green (G) through Yellow (Y) to Red (R), and the farm road light should subsequently turn Green. Each of those transitions should take one clock cycle. The farm road lights are to remain Green for as long as signal Car remains high (1). As soon as signal Car turns low (0), the farm road lights should cycle through Yellow to Red, and then the highway lights should turn Green. Each of those transitions should also take one clock cycle. Note: When the light on one road is green or yellow, the light on the other road must be red. INPUTS: Your Traffic Light Controller (TLC) circuit has one primary input, a sensor, Car, and a periodic clock signal, Cik. OUTPUTS: The circuit should have six traffic light outputs: three for the highway lights (HG, HY, HR) and three for the farm road lights (FG, FY, FR). These signals can be derived directly from the state registers. INITIAL STATE of your circuit is Sq=HG/FR, i.e. Highway green and Farm road red. Synthesize the TLC circuit as a Moore FSM by performing the following tasks: a) Derive and draw the state diagram for your design, using as few states as possible. Use the names used above to create meaningful names for the states, e.g., Sq=HG/FR, etc. b) Encode the states and convert your state diagram to a state transition table. c) Derive the final implementation with a minimum number of logic gates and show the resulting gate-level schematic (you can use any type of logic gates as needed). d) Using the minimized logic solution from item 3 above, implement the circuit as a PLA. Clearly show the content of the PLA and how its inputs and outputs are connected to the state registers to form the sequential machine