Part 2 (22 marks): Assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline, full orwarding, and a predict-taken branch predictor. However, in the code below the actual branch resolution is not as your predictor (see below). Remark: the only forwarding allowed here is: between ID/EX and EX/MEM, and between ID/EX and MEM/W8 pipelined registers lw r2,e(ri) label 1: beq r2,re,label2 # not taken once, then taken lw r3,0 (r2) beq r3,re, label1 # taken add r1,r3,r1 labe12: sw r1,0(r2) (4 marks): Draw the pipeline execution diagram for this code, assuming there are no delay slots and that branches execute (resolve) in the EX stage. Discuss what the impact of this strategy on a MIPS architecture is. Which branch prediction strategy are you now executing? is this the best you can do? 1 2 (4 marks): Now repeat by using delay slots. In the given code, the instruction that follows the branch is the delay slot instruction for that branch. Is this strategy better or worse than the previous one for a MIPS 5-stages pipeline? 4 (7 marks): For the given code, what is the speedup achieved (compare only with Part 1) by moving branch execution into the IF stage? What type of mechanism can be used to achieve the above? Please draw a pipeline diagram. In your speedup calculation assume that the additional comparison in the IF stage does not affect clock time. Also sketch 2 different types of hardware (one simple as in the sections above and one more refined) that can support our moving the decision in IF stage and fully describe and illustrate those. Hint: use ideas from the branch prediction strategy section. 5 (7 marks): We are given the following branch predictors: (1,2), (2, 2), (3, 1), (3, 2), and (2,3). We may select for these predictors to be either local or global. Which onels) would you choose for the snippet of the code above and why? Would you make these predictors local or global? Assume that this snippet of code is in an infinite while loop and assume that we have already reached a stable state. SOLUTION