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Part 3 Digital clock with pushbutton presetting Modify your design as follows: the initial (or starting) time is preset by two pushbuttons when SW[0] is

Part 3 Digital clock with pushbutton presetting

Modify your design as follows: the initial (or starting) time is preset by two pushbuttons when SW[0] is HIGH: one pushbutton KEY[2] is used to set hour (hour +1 whenever KEY[2] is pressed once), another pushbutton KEY[1] is used to set minute (minute+1 whenever KEY[1] is press once). When SW[0] is LOW, the circuit works as a normal clock (counting each second).

hint: make the following changes to part 1 Verilog code:

1)Add the following two always blocks in your part 1 Verilog code: one for hour setting, one for minute setting.

2)Replace SW[15:0] signals with h1, h0, m1, m0.

3)Change SW[17] to SW[0].

//------------------------Please complete the verilog code below----------------------------//

Please complete the following code for Pre_lab

module lab4_2 ( CLOCK_50, SW, KEY,

HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7)

input

output

reg [3:0] temp_h1, temp_h0, temp_m1, temp_m0, temp_s1, temp_s0;

reg [3:0] h1, h0, m1, m0;

// generate 1Hz clock by instantiating module clock

//display time on HEX7 HEX2, HEX1, HEX0 by instantiating seg7

// set minutes

always @ (posedge KEY[1])

begin

m0 = m0+1;

if(m0==10)

begin

m0 = 0;

m1 = m1+1;

end

if(m1 == 6) m1=0;

end

// set hours

always @ (posedge KEY[2])

begin

h0 = h0+1;

if(h0==10)

begin

h0 = 0;

h1 = h1+1;

end

if(h1 == 2 && h0==4)

begin

h1=0;

h0=0;

end

end

// always block for time counter mod-60

endmodule

//------------------------Please complete the verilog code above----------------------------//

Implementation

1)_______Create a new project, and add clock.v and seg7.v to your project.

2)_______Write Verilog files (lab4_2.v) by modifying lab4_1.v.

3)_______Download DE2_pin_assignments.qsf from altera website.

4)_______In Quartus II, select assignments import assignments, choose DE2_pin_assignments.qsf in the file box.

5)_______Compile your design.

6)_______Tools programmer, download the circuit into FPGA, and test the functionality.

7)_______Make a record of the test result.

Part IV Optional with bonus points.

See class notes

Use two switches SW[1] SW[0] for setting/running mode control.

00=set secs

01=set mins

10=set hrs

11=running

In the setting mode, use up / down keys (KEY[0] and KEY[1]) for +1/-1 operations.

The clock frequency for continuous +1/ -1 operations (while the keys are pressed) is 10Hz. Modify the frequency division module to have 10Hz clock from 50MHz clock.

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