PART A. Match Column A with Column B Choose... machine cycle Dynamic studies Choose... Family Concept Choose... Superscalar Choose... superpipeline Choose... RISC Choose... loop buffer Choose... register to register Choose... Choose... Choose... Choose... pipeling Instruction level parallelism Reduced Inst Set of computers CISC Microprogrammed control unit Registers Choose... Choose... Choose... Indi cycle Choose... Choose... CPU uses these to have some working space (temporary storage) This architecture gives emphasis on optimizing the instruction pipeline refers to the degree to which the instructions of a program can be executed in parallel. A means of introducing parallelism into the essentially sequential nature of a machine-instruction program is one in which multiple independent instruction pipelines are used. Each pipeline consists of multiple stages, so that each pipeline can handle multiple instructions at a time Very fast memory and Maintained by fetch stage of pipeline defined to be the time it takes to fetch two operandsfrom registers, perform an ALU operation, and store the result in a register May require more memory access to fetch operands Introduced by IBM with its System/360 in 1964, followed shortly thereafter by DEC, with its PDP-8. this architecture has more addressing modes exploits the fact that many pipeline stages perform tasks that require less than half a clock cycle. An operation where simple LOAD and STORE operations accessing memory are measured during the execution of the program and counting the number of times some feature has appeared or a particular property has held true Suggested by Wilkes in 1951 and introduced by IBM on the S/360 line in 1964. It eases the task of designing and implementing the control unit and provides support for the family concept. its feature is the use of compiler technology to optimize register use