Part A You must develop your own custom peripheral on FPGA and attach it to the embedded ARM processor on the Xilinx ZYNQ SOC via the AXI bus. The task is to implement an image filter (a convolution operation) in programmable logic. You may choose to implement any filter you like, but you must include the following features and functionality: The filter should be 3x3, 5x5, or 7x7 in size. Filter coefficients are stored within the peripheral. Image data is written to the peripheral, and filtered image data is read from the peripheral. Full source image must be stored in the memory of the embedded processor using PGM/PCM format. It must be at least 512x512 pixels in size, An algorithm written in embedded C divides the image appropriately, sends it to the filter peripheral, reads filtered data back, and puts a filtered version of the full image back together. Send the filtered image to the PC and display it alongside the original one. To achieve full marks, you are required to implement at least one of the following advanced features. For example, to make your design more useful or increase its performance, you may choose from: Moving more of the functionality from software to hardware. Adding FIFOs to improve throughput of data in your peripheral. Making the filter function programmable. Making the filter size programmable.