Part B: Multi Cycle Processor

$1.$ Copy the multicycle processor datapath $($Figure B$),$ so there are $2$ datapath

figures.

$2.$ For each figure, assuming Lab$2.$asm runs on the multicycle processor, draw the

datapath AND write the values of the control signals for the following

instructions:

a$.$

Figure $1.$ Process in cycle $19.$

b$.$

Figure $2.$ Process in cycle $33.$

$3.$

Make sure to:

a$.$ label the instruction for each figure.

b$.$ write the corresponding RTL statement$($s$)$ for the instruction during the

cycle based on Table $1.$

c$.$ write the control values next to the labels in the figure $($the name of the

control signal $-$ do NOT write the control values in a separate table$).$

There are altogether $12$ control values. For the Operation, just write the

ALU operation, e$.$g$.$ ADD, SUB, etc. $-$ not in the format of bit value.

$4.$ Make sure the file format to submit is a PDF file only $($ONE file only$).$

rIyUIE D$.$ IVIUILICyLIE rIULESSUI DULUNULI

Hint:

Identify the instruction and the specific process during the specified cycle.

Identify the relevant RTL statements, and the datapath of the identified instruction$/$process$.$

The datapath follows the instruction class datapath, i$.$e$.,\frac{R}{l}\frac{?}{?}\frac{J}{l}oa\frac{d}{?}$ store

Table $1$: RTL statements

$\backslash$table$[[$Step name,$\backslash$table$[[$Action for R$-$type$],[$instructions$]],\backslash$table$[[$Action for memory$-$reference$],[$instructions$]],\backslash$table$[[$Action for$],[$branches$]],\backslash$table$[[$Action for$],[$jumps$]]],[$Instruction fetch,IR$=$ Memory PC$],[,$PC$=$PC$+4],[\backslash$table$[[$Instruction$],[$decode$/$register fetch$]],$A$=$Reg$[$R$[25-21]]],[,$ALUOut $=$ PC $+($sign$-$extend $($IRExecution$,$ address,ALUOut $=$ A op B$,$ALUOut $=$ A $+$ sign$-$extend,if $($A$==$B$)$ then,PC$=$PC$[31-28]||],[\backslash$table$[[$computation$,$ branch$/],[$jump completion$]],,($IR$[15-0]),$PC$=$ALUO,$($IRtable$[[$jump completion$],[$Memory access or R$-$type$],[$completion$]],$Reg$[$R$[15-11]]=,$Load: MDR $=$ Memory$[$ALUOut$],,],[$ALUOut$,\backslash$table$[[$or$],[$Store: Memory $[$ALUOut$]=$ B$]],,],[$Memory read completion,,Load: Reg$[$IR$[20-16]]=$ MDR$,,]]$