Part IV-12-bit Register and Hex-to-Seven Segment Converters In this part, you will implement a memory /register circuit on the Intel DE10-Lite board. The circuit has the following specifications: The current value of switches SW[9.0] on the DE10-Lite board should always be displayed in hexadecimal on the three seven-segment displays HEX2-HEX0. This part of the circuit will be combinational logic. Create a symbol for your binary to hexadecimal circuit. This combinational circuit should take a 4-bit binary input and output the seven-segment display driver signals so that the corresponding hexadecimal digit is displayed. (0 123456789 AbCdEF). It will be convenient to use buses for your inputs and outputs as shown in Figure 4 Create a 12-bit positive edge triggered register using the embedded D flip-flops in the Altera FPGA. (Use the DFF component in the Altera library). Create a symbol for your register. (You can also implement this using 4-bit registers, if you prefer). Again, use buses for your input and output to minimize wiring, as shown in Figure 4. Use KEYTO as an active-low asynchronous reset and KEYII] as the clock input of your 12-bit register. three seven-segment displays HEXS-HEX3. required. If you don't use the red LEDs, they should be turned off. The contents of the 12-bit register should always be displayed in hexadecimal on the .You can display the SW[I input signals on the red LEDs (LEDRID, but this is not Part IV-12-bit Register and Hex-to-Seven Segment Converters In this part, you will implement a memory /register circuit on the Intel DE10-Lite board. The circuit has the following specifications: The current value of switches SW[9.0] on the DE10-Lite board should always be displayed in hexadecimal on the three seven-segment displays HEX2-HEX0. This part of the circuit will be combinational logic. Create a symbol for your binary to hexadecimal circuit. This combinational circuit should take a 4-bit binary input and output the seven-segment display driver signals so that the corresponding hexadecimal digit is displayed. (0 123456789 AbCdEF). It will be convenient to use buses for your inputs and outputs as shown in Figure 4 Create a 12-bit positive edge triggered register using the embedded D flip-flops in the Altera FPGA. (Use the DFF component in the Altera library). Create a symbol for your register. (You can also implement this using 4-bit registers, if you prefer). Again, use buses for your input and output to minimize wiring, as shown in Figure 4. Use KEYTO as an active-low asynchronous reset and KEYII] as the clock input of your 12-bit register. three seven-segment displays HEXS-HEX3. required. If you don't use the red LEDs, they should be turned off. The contents of the 12-bit register should always be displayed in hexadecimal on the .You can display the SW[I input signals on the red LEDs (LEDRID, but this is not