Part1: Direct Mapped Cache, b = 1 word

Assume that you have a system that contains a 16 -word cache (C=16). Consider the following RISCV assembly code addi t0, zero, 4 addi s0, zero, 0 loop: beq to, zero, done Iw tl, 030(so) Iw t2, 0x70(s0) Iw t3, 0x54(s0) Iw t3,050(s0) addi t0, t0, 1 j loop done: 3) Find the miss rate (NOTE: if the number is 88.777778, then your answer should be 88.8 ): (Note: number of misses includes both compulsory and the conflict misses in all iterations) Cache miss rate= %