PCSro WB ControlM WB EX FND Add Shitdd Ado left 2 Read register 1 Read Zero ALU ALU Read Wribe gister Registers Readt Address Data 15-01 Sign32 6 ALL MemRead 20-16 [15-11] RegDst FIGURE 4.51 The pipelined datapath of Figure 4.46, with the control signals connected to the control portions of the pipeline registers. The control values for the last three stages are created during the instruction decode stage and then placed in the ID/EX pipeline register. The control lines for each pipe stage are used, and remaining control lines are then passed to the next pipeline stage