PERFORM THIS IN LTSPICE AND PROVIDE ANSWERS PLEASE GAURANTEED THUMBS UP

1. Let's build a NAND gate. Save your inverter with a new name like CMOS_NAND, and duplicate your nmos and pmos devices, and connect biasing as required. Note that the body terminals of all pmos devices need to be connected to VDD, and the body terminals of all nmos devices are connected to ground. Add a 10pF capacitor at VOUT, which simulates the apparent capacitance of one MOSFET; this simulates the effect of another MOSFET connected to the output, which would be the case if your NAND gate was driving another logic gate. Your circuit should look something like the circuit below. 2. Specify each voltage source as a piecewise linear (PWL) source, which allows us to apply an arbitrary waveform to simulate a digital signal. Control-right click on one input voltage source, called VA-SRC in the schematic below, and specify VALUE to be: PWL (0 0 48u 050u5148u5150u0198u0200u5248u5250u0348u0350u 5) For the second input voltage source specify VALUE to be (all one line - no line breaks): 0398u0400u5) These will provide two "random" digital signals to inputs A and B of the NAND gate with a fundamental frequency of 10kHz. You will need to specify a transient simulation with an appropriate stop time like 0.5ms using tran 0.5m. 3. Simulate the circuit, and plot the voltage and VA and VB. Notice that the waveforms approximate two different digital inputs. Then also plot the output VOUT. Save the Increase the effective trequency to 10MHz by changing the PWL values for VA-SRC and VB-SRC to (no line breaks): You will also need to change the stop time for the simulation to something like 0.5s. Resimulate the circuit and save the plot. Note the voltage spikes at the output and what ooks like an RC time constant during output transitions due to the effective RC circuit Formed by the capacitance of the transistor gates and the channel resistances (which you calculated in Part 1)