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RISC-V is an open source hardware instruction set originally developed at UC Berkeley It supports 3 word widths, 32, 64, 128 bits. One of its characteristics is to have a subset of compressed instructions utilizing 16 bits, used to reduce program size when intermixed with the regular instructions. In this project, tour team will design the hardware component (Thumb mini micro processor) required to execute some of these instructions. This project is to be performed either individually or by a group of at most 4 students. Use the VHDL compiler or the graphical designer and simulator to design tiny processor able to execute a subset of the compressed RISC-V instruction set in accordance with the specifications below. For this project, you are to design (using VHDL and components design or schematics capture) and simulate an 8-bit processor (8-bit registers), which includes two registers RI and R2, able to execute the instruction set shown on table 1. Table RISC-V Compressed Instruction subset Mnemonic Action 15 14 13 12 11 10 9N76543210 LI Rd,imm Load Rd with immediate 010 imm5 rd imm4:0 01 SRLI Riimm Shift right Ri by imm bits 100 imm500 rs/rd imm4:0 01 ANDI Riimm Logical product Ri with imm 100 mm 10 s/rd imm4: 001 SUBW Rd, Rs2 Subtract Rd minus RS2 1001 11 rs/rd 002 01 OR Rd, Rs2 Logical sum of Rd and Rs2 100 0 11 r/rd 105201 SLLI Ri.imm Shift lett Riby imm bits 000 mm rs/rd imm4:0 10 ADDW Rd,R2 Add Rd plus RS2 100 1 11 s/d 012 01 MV Rd.Rs Copy Rs to Rd 100 0 rd TS 10 OUT Rs Displays contents of Rs 100 000 000 s 11 Rs: source register: Rd: destination register: Ri = 001,010 "Not part of the RISC-V standard The block diagram of the micro RISC-V processor is shown on Figure 1. The machine has 18 input signals and 8 output signals. The 18 input signals consist of 16 bits used for instructions and 2 extra bits used to clock the operations: one clock signal will command the execution of the operation EXE) and the other will uxlate the destination register (UPD) (these two bits cannot be zero at the same time). The 8 output bits should show the value contained in R1 (in binary format), except when instructed to do it differently by the instruction OUT Coding example: LIRI,5 LI R2,13 in binary 0100 0000 1001 0101 in binary 0100 0001 00110101 Thumb mini micro processor ADD RI.R2, R i n binary 1001 1100 1010 1001 VERY IMPORTANT: 1. Clock signals activate circuit components when they are zero. Project report: Une computer word processing and drawing tools of your choice to generate your report It must consist of the following items: 1. Block diagram (planned drawing) of the circuit implementation (show major components like registers, logic units, multiplexers, connections, etc.). 2. Printout of the circuit schematics (from Quartus) or VHDL code used to implement the design. 3. Electronic copy of the vhd or the.bdf file required to run the simulation 4. Brief report on the simulation results (which instructions were simulated and success or not of the functionality of the design). Make sure to run a simulation that loads values in the registers before trying any operation such as ADD or SHIFT. RISC-V is an open source hardware instruction set originally developed at UC Berkeley It supports 3 word widths, 32, 64, 128 bits. One of its characteristics is to have a subset of compressed instructions utilizing 16 bits, used to reduce program size when intermixed with the regular instructions. In this project, tour team will design the hardware component (Thumb mini microprocessor) required to execute some of these instructions This project is to be performed either individually or by a group of at most 4 students. Use the VHDL compiler or the graphical designer and simulator to design tiny processor able to execute a subset of the compressed RISC-V instruction set in accordance with the specifications below. For this project, you are to design (using VHDL and components design or schematics capture) and simulate an 8-bit processor (8-bit registers), which includes two registers RI and R2, able to execute the instruction set shown on table 1 Table RISC-V Compressed Instruction subset Mosmonle Action 15 14 13 12 11 10 9876543210 LI Rd.imam Load Rd with immediate 010 imm5 d imm 4: 00 SRLI Riimm Shift right Ri by imm bits 100 imm500 rsd imm :00 ANDI Ri imm Logical product Ri with imm 100 mm 10 rund imm4- 001 SUBW Rd.Rs2 Subtract Rd minus RS2 100 1 1 0 0 rs2 01 OR Rd.RS2 Logical sum of Rd and R2 1000 11 rund lio ir 2 101 SLLI Ri.imm Shift lett Riby im bits 0:00 lim d imm to 10 ADDW Rd.Rs2 Add Rd plus Rs 2 100111 201 MV RdRs Copy Rsto Rd 1000 rd S 10 OUT Rs Displays contents of Rs 100 0 00 000 11 Rs: source register: Rd: destination register, Ri = 001,010 "No part of the RISC-V standard The block diagram of the micro RISC-V processor is shown on Figure 1. The machine has 18 input signals and 8 output signals. The 18 input signals consist of 16 bits used for instructions and 2 extra bits used to clock the operations: one clock signal will command the execution of the operation (EXE) and the other will update the destination register (UPD) (these two bits cannot be zero at the same time). The 8 output bits should show the value contained in RI (in binary format), except when instructed to do it differently by the instruction OUT Coding example: LIRIS LIR2.13 in binary 0100 0000 10010101 in binary 0100 0001 0011 0101 That mini| VITY ADD RI.R2RI in binary 1001 1100 1010 1001 VERY IMPORTANT: 1. Clock signals activate circuit components when they are zero. Project report: Use computer word processing and drawing tools of your choice to generate your report It must consist of the following items! 1. Block diagram (planned drawing) of the circuit implementation (show major components like registers, logic units, multiplexers, connections, etc.). 2. Printout of the circuit schematics (from Quartus) or VHDL code used to implement the design. 3. Electronic copy of the .vhd or the.bdf file required to run the simulation. 4. Brief report on the simulation results (which instructions were simulated and success or not of the functionality of the design). Make sure to run a simulation that loads values in the registers before trying any operation such as ADD or SHIFT. RISC-V is an open source hardware instruction set originally developed at UC Berkeley It supports 3 word widths, 32, 64, 128 bits. One of its characteristics is to have a subset of compressed instructions utilizing 16 bits, used to reduce program size when intermixed with the regular instructions. In this project, tour team will design the hardware component (Thumb mini micro processor) required to execute some of these instructions. This project is to be performed either individually or by a group of at most 4 students. Use the VHDL compiler or the graphical designer and simulator to design tiny processor able to execute a subset of the compressed RISC-V instruction set in accordance with the specifications below. For this project, you are to design (using VHDL and components design or schematics capture) and simulate an 8-bit processor (8-bit registers), which includes two registers RI and R2, able to execute the instruction set shown on table 1. Table RISC-V Compressed Instruction subset Mnemonic Action 15 14 13 12 11 10 9N76543210 LI Rd,imm Load Rd with immediate 010 imm5 rd imm4:0 01 SRLI Riimm Shift right Ri by imm bits 100 imm500 rs/rd imm4:0 01 ANDI Riimm Logical product Ri with imm 100 mm 10 s/rd imm4: 001 SUBW Rd, Rs2 Subtract Rd minus RS2 1001 11 rs/rd 002 01 OR Rd, Rs2 Logical sum of Rd and Rs2 100 0 11 r/rd 105201 SLLI Ri.imm Shift lett Riby imm bits 000 mm rs/rd imm4:0 10 ADDW Rd,R2 Add Rd plus RS2 100 1 11 s/d 012 01 MV Rd.Rs Copy Rs to Rd 100 0 rd TS 10 OUT Rs Displays contents of Rs 100 000 000 s 11 Rs: source register: Rd: destination register: Ri = 001,010 "Not part of the RISC-V standard The block diagram of the micro RISC-V processor is shown on Figure 1. The machine has 18 input signals and 8 output signals. The 18 input signals consist of 16 bits used for instructions and 2 extra bits used to clock the operations: one clock signal will command the execution of the operation EXE) and the other will uxlate the destination register (UPD) (these two bits cannot be zero at the same time). The 8 output bits should show the value contained in R1 (in binary format), except when instructed to do it differently by the instruction OUT Coding example: LIRI,5 LI R2,13 in binary 0100 0000 1001 0101 in binary 0100 0001 00110101 Thumb mini micro processor ADD RI.R2, R i n binary 1001 1100 1010 1001 VERY IMPORTANT: 1. Clock signals activate circuit components when they are zero. Project report: Une computer word processing and drawing tools of your choice to generate your report It must consist of the following items: 1. Block diagram (planned drawing) of the circuit implementation (show major components like registers, logic units, multiplexers, connections, etc.). 2. Printout of the circuit schematics (from Quartus) or VHDL code used to implement the design. 3. Electronic copy of the vhd or the.bdf file required to run the simulation 4. Brief report on the simulation results (which instructions were simulated and success or not of the functionality of the design). Make sure to run a simulation that loads values in the registers before trying any operation such as ADD or SHIFT. RISC-V is an open source hardware instruction set originally developed at UC Berkeley It supports 3 word widths, 32, 64, 128 bits. One of its characteristics is to have a subset of compressed instructions utilizing 16 bits, used to reduce program size when intermixed with the regular instructions. In this project, tour team will design the hardware component (Thumb mini microprocessor) required to execute some of these instructions This project is to be performed either individually or by a group of at most 4 students. Use the VHDL compiler or the graphical designer and simulator to design tiny processor able to execute a subset of the compressed RISC-V instruction set in accordance with the specifications below. For this project, you are to design (using VHDL and components design or schematics capture) and simulate an 8-bit processor (8-bit registers), which includes two registers RI and R2, able to execute the instruction set shown on table 1 Table RISC-V Compressed Instruction subset Mosmonle Action 15 14 13 12 11 10 9876543210 LI Rd.imam Load Rd with immediate 010 imm5 d imm 4: 00 SRLI Riimm Shift right Ri by imm bits 100 imm500 rsd imm :00 ANDI Ri imm Logical product Ri with imm 100 mm 10 rund imm4- 001 SUBW Rd.Rs2 Subtract Rd minus RS2 100 1 1 0 0 rs2 01 OR Rd.RS2 Logical sum of Rd and R2 1000 11 rund lio ir 2 101 SLLI Ri.imm Shift lett Riby im bits 0:00 lim d imm to 10 ADDW Rd.Rs2 Add Rd plus Rs 2 100111 201 MV RdRs Copy Rsto Rd 1000 rd S 10 OUT Rs Displays contents of Rs 100 0 00 000 11 Rs: source register: Rd: destination register, Ri = 001,010 "No part of the RISC-V standard The block diagram of the micro RISC-V processor is shown on Figure 1. The machine has 18 input signals and 8 output signals. The 18 input signals consist of 16 bits used for instructions and 2 extra bits used to clock the operations: one clock signal will command the execution of the operation (EXE) and the other will update the destination register (UPD) (these two bits cannot be zero at the same time). The 8 output bits should show the value contained in RI (in binary format), except when instructed to do it differently by the instruction OUT Coding example: LIRIS LIR2.13 in binary 0100 0000 10010101 in binary 0100 0001 0011 0101 That mini| VITY ADD RI.R2RI in binary 1001 1100 1010 1001 VERY IMPORTANT: 1. Clock signals activate circuit components when they are zero. Project report: Use computer word processing and drawing tools of your choice to generate your report It must consist of the following items! 1. Block diagram (planned drawing) of the circuit implementation (show major components like registers, logic units, multiplexers, connections, etc.). 2. Printout of the circuit schematics (from Quartus) or VHDL code used to implement the design. 3. Electronic copy of the .vhd or the.bdf file required to run the simulation. 4. Brief report on the simulation results (which instructions were simulated and success or not of the functionality of the design). Make sure to run a simulation that loads values in the registers before trying any operation such as ADD or SHIFT