Pipeline

1) Describe the decode phase. Mention what are the operands of each type of instruction (load, store, r-format, beq) Give the size of the involved inter-stage (phase) registers.

2) Consider the following MIPS assembly code:

sw $s1, 48(%s0)

add $t1, $t2, $t3

beq $s4, $s5 Loop

sub $t4, $s2, $t5

sll $t1, 4

What will be the performance of executing the above 5 instructions in a single-cycle implementation if:

Accessing (using) Memory Units takes: 250 ps

Register File takes: 200 ps

Main ALU takes: 200 ps

Note: accessing the other unit is considered to take no time;

3) Mention the three types of hazards that can occur in pipelining, and give a brief description of them.

Describe the write-through policy and explain the use of it.

4) Find the total number of bytes for a direct mapping cache to store 512KB of data in 4 words blocks assuming a 32-bit address and word addressing. Explain your answer. Note: 1K = 1024