Please answer all parts of question - dont have to be lengthy responses! Thank you

Examine the Verilog HDL model of the clock_gen module that is shown below. Show an equivalent desisn for this module that uses a single binary counter and some gating (and/or latching). Do t // This module generates the scan and debounce clocks pulses // that are derived from the 50 Mhz Input clock on the DE2-115 // board using clock division methods module clock_gen(cik in, scan_en, scan_clk, debounce_clk): input clk in, scan_en: output scan_cik, debounce_clk: reg (i6:01 count: assign scan clk = (scan en) ? count [16] : scan clk; assign debounceclk -count [121: always (posedge clk_in) begin countcount1: end endmodule For the clock_gen module above, given that the clk_in input is a 50 Mhz clock source what is the frequency of the scan clk and debounce clk signals that are produced? For the clock_gen module, how does the scan_en signal affect the scan_clk? How does it affect the debounce clk? Why do we need a debounce circuit in this design What factors should one consider when choosing the frequencies of clock_gen module out put clock signals? Would these values be appropriate for all mechanical push button nor mally open/monetarily closed devices? Why or why not