Please Answer all questions and explain them. Thank you!
Assume that the company that you are employed is developing a hardwired control unit for a new processor. Given the data path and instruction formats/encodings shown below, synthesize the sequence of control signals and state machines to solve the following instruction set implementation problems. The data path you are to use and the instruction formats are: where: the type of the instruction (F1 or F2) is determined by the opcode; S controls the setting of condition codes (0-no, 1-yes); and I is an index bit that controls operand addressing for instructions as follows: - For instructions of type F1: if I=0 then operand1 is GPR [RS1] and operand2 is the contents GPR [RS2]; and if I=1 then operand1 is GPR [RS1] and operand2 is the contents MM [GPR [RS2]+PC - For instructions of type F2: if I=0 then operand1 is GPR [Rd] and operand2 is the contents MM[sign_extended(IR. offset) ]; and if I=1 then operand1 is GPR[Rd] and operand2 is the contents MM [sign_extended (IR.offset) +PC ] The data path has two temporary latches (Tmp1 and Tmp2) for use by the implementation (they are not visible to the user). Furthermore, in this machine, you may assume that the program counter is stored as GPR [R7] and that GPR [R0] always holds the value of 0 . The stack is stored in memory and is pointed to by the stack pointer SP. The stack grows to smaller addresses. This is a 16-bit machine with a byte addressable memory. You can assume that the ALU supports any arithmetic operation to support your needs to answer the questions below. 1. (16 points) Develop a complete solution to fetch instructions into the IR. You can assume that there are conditions F1 and F2 that denote the presence of an instruction of the corresponding type that you have placed in the IR. You can define whatever control signals you need to load bits from the bus into the IR. Be certain to define specifically what operations those control signals enable. 2. (4 points) Develop the control signals to fetch and store operand 1 into Tmp1 for instruction type F1. Call this the D1 state. 3. (4 points) Develop the control signals to fetch and store operand 1 into Tmp1 for instruction type F2. Call this the D2 state. 4. (4 points) Develop the control signals to fetch and store operand 2 into Tmp2 for instruction type F1 when IR.I=0. Call this the D3 state. 5. (6 points) Develop the control signals to fetch and store operand 2 into Tmp2 for instruction type F1 when IR.I=1 . Call this the D4 state. 6. (4 points) Develop the control signals to fetch and store operand 2 into Tmp2 for instruction type F2 when IR.I=0. Call this the D5 state. 7. (6 points) Develop the control signals to fetch and store operand 2 into Tmp2 for instruction type F2 when IR.I=1 . Call this the D6 state. 8. (12 points) Assume: (i) an execute state (E1) has been defined that executes instructions of type F1; (ii) an execute state (E2) has been defined that executes instructions of type F2; and (iii) that branches are of no concern. Build the finite state machine to transition between the above states to process the instructions in this machine. 9. (8 points) Implement a sequential circuit for the state machine you developed for the previous problem. You can only use flip-flops, decoders, and and, or, and not gates. 0. (6 points) Assume that you are to add a timeout trap to state T1. The machine should transition to this state when (a) it finishes execution of the current instruction and (b) the PSW.P bit is clear and (c) the TRAP signal is true. Modify your state machine to incorporate this trap condition. 1. (6 points) Assume that the P SW. P bit denotes privileged/user modes of execution ( 0 -user, 1-privileged). Modify your state machine to implement a trap when a privileged instruction is attempting to be executing when the machine is in user mode. You can assume that there is a signal PRIV coming from the IR. opcode decoder denoting that the instruction is privileged (PRIV==1) or not (PRIV==0). Only F1 instructions need to be tested for privileged status. This trap must be caught immediately after the fetch operation for F1 instructions is complete
