PLEASE ANSWER ALL QUESTIONS, I DON'T KNOW MUCH ABOUT THIS SUBJECT...

1) Find and describe the cache configuration in your mobile phone CPU and in your computer CPU (laptop)? How many levels is the cache? Give details for L1 instruction and data caches? Number of blocks, associativeness, write system. 2) Answer the following questions. Show your calculations. a) A 64Kbyte data, 8-word block, direct-mapped cache has blocks. b) A 64Kbyte data, 8-word, 2-way set associate cache has sets. c) Assume that we are given a direct-mapped cache of 16-blocks, where each block has 4 words. Memory byte address 1025 corresponds to block index d) Assume that we are given a 4-way set associative cache of 16-blocks, where each block has 4 words (1 word 4 bytes). Memory byte address 1025 corresponds to set index 3) Assume a program executes 106 (1 million) instructions. 25% of instructions are loadstore. The miss rate of the instruction cache is 4% and the miss rate of the data cache is 10%. If processor has a CPI of 1.5 without any memory stalls. The miss penalty is 50 clock cycles (in CPU clock). See example in page 477 in texbook 4th Ed. Determine a) the total miss cycles for instructions b) the total miss cycles for data (load-stores) c) the total memory-stall cycles. d) the CPI with miss rate e) what is the execution time if the CPU clock is 2.0GHz. 4) A cache 4K blocks, 4096, a 4-word block, and 32 bit address. Find the total number of sets and the tag bits for caches directly mapped, two-way, four-way set associative, and fully associative