Please answer the following about the data cache memory in the figure below that is accessed by psysical address.

$1)$ How many bytes is one block in the data cache memory represented in the diagram? And what is the reason that this cache can improve computer performance, specifically memory access time?

$2)$ What is the cache mapping method used in the given cache, and what does the term "write$-$update" refer to$?$

$3)$ If the total data size stored in the cache remains the same while converting one block to $2$ words, what would be the number of bits for the tag?

$4)$ If the total data size stored in the cache remains constant while converting it to a $2-$way set associative mapping, what would be the number of bits for the tag?

$5)$ If the virtual address is $32$ bits and the page size is $4$k bytes, how many bits of the physical page number should the page table return?