PLEASE ATTACH ALL SCHEMATICS & DIADRAMS AS A PICTURE. THANKS!!

a.

(10 pts) Consider the following two System Verilog modules.

• Do they have the same function?
• Sketch the circuit schematic each one implies.

b.

(12 pts) Sketch the state transition diagram for the FSM described by the following HDL code. Draw a state diagram for this Moore machine making sure to label and specify the outputs for each state. Include and label all possible state transition arcs, including self-transitions.

module fsm( input logic clk,

input logic reset,

input logic a, b,

output logic y );

typedef enum logic[1:0] {S0, S1, S2, S3} statetype;

statetype state, nextstate;

always_ff @( posedge clk, posedge reset)

begin

if( reset )

state <= S0;

else

state <= nextstate;

end

always_comb

case(state)

S0: if (a^b) nextstate = S1;

else nextstate = S0;

S1: if (a&b) nextstate = S2;

else nextstate = S0;

S2: if (a|b) nextstate = S3;

else nextstate = S0;

S3: if (a|b) nextstate = S3;

else nextstate = S0;

default: nextstate = S0;

endcase

assign y = (state == S1) | (state == S2);

endmodule