Please be neat and thorough and will rate promptly!

Thanks

(20 points) Consider the RISC computer (byte-addressable with 32-bit words) with a 5-stage pipelined data path. Registers R4, R5, and R6 initially contain 10, 50, and 55, respectively. Assume the first instruction of the following program is fetched in clock cycle 1 and the remaining instructions are fetched in the successive cycles. The memory address of the first instruction is 800 All the numbers are in decimal. What are the contents (in decimal) of IR, PC, RA, RB, RZ, RY, and R6 in the pipeline after cycles 1 to 8? Note that we said "stage" in Problem 1, because we considered only one instruction there Use X for any unknown values. For IR, Just use the symbolical opcode (e.g., Subtract, Store, etc; No need to write the entire instruction like "Subtract R6, R5, #1"). Assume that dynamic branch prediction (instead of delayed branching) is used in this computer to eliminate the one-cycle branch delays and any subsequent instructions fetched after a branch get discarded (i.e., processing stopped in the pipeline), if (and after) the branch prediction is determined wrong. Also assume operand forwarding is used to handle data dependencies, if any. Hint: You can find the sequence of actions of Load and Store in Section 5.4 of the textbook. R6, R5, #1 R5, 60(R4) START R4, R5, R6 R5, 10(R4) START: Subtract Store Branch _if [R51 IR4] Add Load Other instructions Cycle Cycle 2Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 IR PC RA RB RZ RY R6 (20 points) Consider the RISC computer (byte-addressable with 32-bit words) with a 5-stage pipelined data path. Registers R4, R5, and R6 initially contain 10, 50, and 55, respectively. Assume the first instruction of the following program is fetched in clock cycle 1 and the remaining instructions are fetched in the successive cycles. The memory address of the first instruction is 800 All the numbers are in decimal. What are the contents (in decimal) of IR, PC, RA, RB, RZ, RY, and R6 in the pipeline after cycles 1 to 8? Note that we said "stage" in Problem 1, because we considered only one instruction there Use X for any unknown values. For IR, Just use the symbolical opcode (e.g., Subtract, Store, etc; No need to write the entire instruction like "Subtract R6, R5, #1"). Assume that dynamic branch prediction (instead of delayed branching) is used in this computer to eliminate the one-cycle branch delays and any subsequent instructions fetched after a branch get discarded (i.e., processing stopped in the pipeline), if (and after) the branch prediction is determined wrong. Also assume operand forwarding is used to handle data dependencies, if any. Hint: You can find the sequence of actions of Load and Store in Section 5.4 of the textbook. R6, R5, #1 R5, 60(R4) START R4, R5, R6 R5, 10(R4) START: Subtract Store Branch _if [R51 IR4] Add Load Other instructions Cycle Cycle 2Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 IR PC RA RB RZ RY R6