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Please describe, at a system block-level, why the design of the architecture was chosen in order to achieve the design specifications and functionality that the project asks for?

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The design specifications for the project were:

Design a sequential system that has one synchronous input bit stream X and one output Z, with the following functionality:

1. We look at the 010 and 110 sequences in the input stream. The system outputs the same input stream, except that one clock cycle after any of these sequences (with overlap) have been present at the input the output becomes complemented version of the input, the next sequence ( 010 or 110) to appear in the input returns the output to normal, the next sequence to appear again at the input causes the output to be again a complemented version of the input and so on and so forth.

2. The timing trace below (Moore-type) depict a possible example with various events in order to clarify the prescribed functionality.

3. Discuss any timing problem that you think your design solution may have, and give a possible alternative.

The Design Constraints of the project were:

1. Do not use more than 4 Flip-Flops of any type.

2. Minimize the use of discrete gates, multiplexers or decoders of any type.

3. The system can use any number of subsystems.

The pictures below was the final design choice for the project based on all of the rules and guidelines above.

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Please describe, at a system block-level, why the design of the architecture was chosen in order to achieve the design specifications and functionality that the project asks for?

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We implement a Moore FSM base sequence detector to identify arrival of "010" or "110". The output ZD is set to logic 1 at first occurence of above "010" or "110" input and reset to lofic 0 and second occurence. Hence ZD keeps toggling with "010" or "110" arrival. ZD is logically XORed with input X to give output Z. When ZD = 1 then Z=X' When ZD = 0 then Z = X State graph is shown below We use binary state enoding SY Let so = Q2Q, Q = 000 SI = 001 S2 = 010 S3 = 011 S4 = 100 S5=101 S6=1 to S7 = III We implement design using 3 No's of D Flip Flops, Hence use K-Map to derive D inputs 80100 01 ID 20% OLI 10 10 TTT Dz=QqQq+Q, X+Q2Q, Qo D1 = Q2Q, x+ Q2Q, X+Q, QoX x Qot QA00 OD 10 Q299 00 OD 1L 10 all 10 11 10 Do=X+QQ,+ QLQ , Qo ZI=QQ1 +Q Po State Table STATE PRESENT STATE INPUT NEXT STATE OUTPUT Q1 QOX Q2+ Q1+ Q0+ ZD 00 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 0 0 We implement design using 3 No's of D Flip Flops, Hence use K-Map to derive D inputs ORO Deno Q1 Deno QO Deno CLOCK N We implement a Moore FSM base sequence detector to identify arrival of "010" or "110". The output ZD is set to logic 1 at first occurence of above "010" or "110" input and reset to lofic 0 and second occurence. Hence ZD keeps toggling with "010" or "110" arrival. ZD is logically XORed with input X to give output Z. When ZD = 1 then Z=X' When ZD = 0 then Z = X State graph is shown below We use binary state enoding SY Let so = Q2Q, Q = 000 SI = 001 S2 = 010 S3 = 011 S4 = 100 S5=101 S6=1 to S7 = III We implement design using 3 No's of D Flip Flops, Hence use K-Map to derive D inputs 80100 01 ID 20% OLI 10 10 TTT Dz=QqQq+Q, X+Q2Q, Qo D1 = Q2Q, x+ Q2Q, X+Q, QoX x Qot QA00 OD 10 Q299 00 OD 1L 10 all 10 11 10 Do=X+QQ,+ QLQ , Qo ZI=QQ1 +Q Po State Table STATE PRESENT STATE INPUT NEXT STATE OUTPUT Q1 QOX Q2+ Q1+ Q0+ ZD 00 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 0 0 We implement design using 3 No's of D Flip Flops, Hence use K-Map to derive D inputs ORO Deno Q1 Deno QO Deno CLOCK N