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Format Design for a modified MIPS-Lite ISA Instruction Set Architecture) Design the instruction formats for a version of the MIPS-Lite insiruction set assuming we have a 16-bit word. The instructions that should be supported are: Riype: add. sub, and, or. nor, xor. slt Immediate: addi. andi, ori. xori. Iw, sw. lb. Ibu, sh. lui, beqz, bnez. slti (13 Immed Indeterminate (at this point sll. srl. jr 2 Jump) 3 Rtype or Immediate Jung J. Jal Note: heyz and bnez have the follow ing format: beqz SI. label. Ir SI is equal to zero, branch to label. There are S registers. Memory is byte addressable Our design objectives are to: Have all instructions be one word wide Have a fixed format design (avoid sequential decode . Have as long an immediate as possible for load and store effective aldress calculations (hase register +immediate offset ) Have as long an immediate as possible for reutive branch addressing (PC+ immediate offset). Be able to form a 16-bit immediate efficienily (this requires an 8-bit immediate field and an lui instruction) Support shift and jump register instructions in whichever format has more unused opcode or func values (perhaps not R-type Hint: you do not have to have the same number or type of formats as the MIPS. You do not have to have the same size immediate for different formats Be creative with your designs After you have designed your instruction formats answer the following questions a List your instruction formats Lahel the different fields of each format and show how many bits per field and the location of each field within the instruction word b. What is the rangets) of an unsigned immediate? c. what is the ranges) of a signed immediate? d. What is the range of a conditional branch relative to the next PC (in bytes)? e Show the jump address calculation 1 What is the address offset for memory instructions (lw and sw? Instruction Format Design for a modifiea MIPS-Lite ISA (Instruction Set Architecture) Design the instruction forma o a version of the MIPS-Lite instruction set assuming we have a l6-bit word. The nstructons that should be supported are Re: add. sub, and. or. nor, xor. slt 7 Riype) Immediate: addi. andi. ori. xori. Iw, sw. lb. Ibu. sh. lui. beqz, bnez. slti (13 Immed) Jump: j.jal (2 Jump) (3 Rtype or Immediate sll. srl. jr Note: beyz and bnez have the follow ing forat: e Thee are rees Memory is bye ldsabi Our design objectives are to: S. label SI is equal to zero branch to label. Have all instructions be one word wide. Have a fixed format design (avoid sequential decode). Have as long an immediate as possible for load and store effective address calculations (hase register + immediate offset). Have as long amediate as possible forratve branch addressing (PC +immediate offset). .Be able to o a 6-bit immediaie elficiently this requires an S-hit immediate field and an lui instruction) Support shift and jump registe instructions in wcever format has more unused opcod or func values (perhaps not R-type Hint: you do not have to have the same number or type of formats as the MIPS. You do not have to have the same size immediate for different formats Be creative wit our designs! Alter you have designed your instruction formats answer the following questions. a. List your instruction formats. Label the different fields of each format and show how n any bits per field and the location of each field within the instruction word. h. What is the ranges of an unsigned immediate? c. What is the rangets) of a signed immediate? d. What is the range of a conditional branch relative to the next PC (in bytes)? e. Sho the jump address calculation . What is the address offse for memory instructions (w and sw)? Format Design for a modified MIPS-Lite ISA Instruction Set Architecture) Design the instruction formats for a version of the MIPS-Lite insiruction set assuming we have a 16-bit word. The instructions that should be supported are: Riype: add. sub, and, or. nor, xor. slt Immediate: addi. andi, ori. xori. Iw, sw. lb. Ibu, sh. lui, beqz, bnez. slti (13 Immed Indeterminate (at this point sll. srl. jr 2 Jump) 3 Rtype or Immediate Jung J. Jal Note: heyz and bnez have the follow ing format: beqz SI. label. Ir SI is equal to zero, branch to label. There are S registers. Memory is byte addressable Our design objectives are to: Have all instructions be one word wide Have a fixed format design (avoid sequential decode . Have as long an immediate as possible for load and store effective aldress calculations (hase register +immediate offset ) Have as long an immediate as possible for reutive branch addressing (PC+ immediate offset). Be able to form a 16-bit immediate efficienily (this requires an 8-bit immediate field and an lui instruction) Support shift and jump register instructions in whichever format has more unused opcode or func values (perhaps not R-type Hint: you do not have to have the same number or type of formats as the MIPS. You do not have to have the same size immediate for different formats Be creative with your designs After you have designed your instruction formats answer the following questions a List your instruction formats Lahel the different fields of each format and show how many bits per field and the location of each field within the instruction word b. What is the rangets) of an unsigned immediate? c. what is the ranges) of a signed immediate? d. What is the range of a conditional branch relative to the next PC (in bytes)? e Show the jump address calculation 1 What is the address offset for memory instructions (lw and sw? Instruction Format Design for a modifiea MIPS-Lite ISA (Instruction Set Architecture) Design the instruction forma o a version of the MIPS-Lite instruction set assuming we have a l6-bit word. The nstructons that should be supported are Re: add. sub, and. or. nor, xor. slt 7 Riype) Immediate: addi. andi. ori. xori. Iw, sw. lb. Ibu. sh. lui. beqz, bnez. slti (13 Immed) Jump: j.jal (2 Jump) (3 Rtype or Immediate sll. srl. jr Note: beyz and bnez have the follow ing forat: e Thee are rees Memory is bye ldsabi Our design objectives are to: S. label SI is equal to zero branch to label. Have all instructions be one word wide. Have a fixed format design (avoid sequential decode). Have as long an immediate as possible for load and store effective address calculations (hase register + immediate offset). Have as long amediate as possible forratve branch addressing (PC +immediate offset). .Be able to o a 6-bit immediaie elficiently this requires an S-hit immediate field and an lui instruction) Support shift and jump registe instructions in wcever format has more unused opcod or func values (perhaps not R-type Hint: you do not have to have the same number or type of formats as the MIPS. You do not have to have the same size immediate for different formats Be creative wit our designs! Alter you have designed your instruction formats answer the following questions. a. List your instruction formats. Label the different fields of each format and show how n any bits per field and the location of each field within the instruction word. h. What is the ranges of an unsigned immediate? c. What is the rangets) of a signed immediate? d. What is the range of a conditional branch relative to the next PC (in bytes)? e. Sho the jump address calculation . What is the address offse for memory instructions (w and sw)