Please follow the instructions from the first photo provided, the required code files should also be provided in the photos along with the diagram above needed for the code.

In this lab, you will be required to implement load and store instructions. Pre-Lab: To be done before coming to the lab (CAD simulation). Use Figure 4.24 (page 271) as a reference to implement load and store instructions. You only have to modify the top-level file and port map the components needed to implement the load and store instructions. You can use the register file component to make a small data memory. The MemWrite signal will be connected to where RegWtite is connected in the register file. The memory address, which is the result computed by the ALU should be connected to both the read address port and the write address port. You can ignore the MemRead signal. The MemRead signal will be used only when you have a real DRAM memory. You can modify the register file component to remove the second read port, or just connect place holder signals to the second read port. Note that this memory is word-addressed as opposed to byte addressed. Therefore, array indices should not be multiplied by 4 . Encode and simulate the following program. Initialize registers and data memory with the following values: r1=0;DMem[0]=5;DMem[1]=4. lux2,0(r1) lixr3,1(r1) add r2,r2,r3 swr2,0(r1) use ieee.std_logic_1164.a17; use ieee.std_logic_signed.a71; package components is component ful1add IS PORT ( cin, x,y : IN STD_LOGIC; S, Cout : OUT STD_LOGIC ); END component; component ripple_carry IS PORT ( Cin: IN STD_LOGIC; x,y : IN STD_LOGIC_VECTOR (3 downto 0); S: OUT STD_LOGIC_VECTOR ( 3 downto 0); COut : OUT STD_LOGIC ); END component; component mux2to1 Is generic(n : integer :=4); PORT ( s: IN std_logic; a, b : in std_logic_vector ((n1) downto 0); f: :UT std_logic_vector ((n1) downto 0)) END component; component mux4to1 IS generic ( n : integer:= 4); PORT ( w0,w1,w2, w3 : IN STD_LOGIC_VECTOR ((n1) downto 0 ); S : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0); f : OUT STD_LOGIC_VECTOR ((n1) downto 0)); END component; component dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR (1 DOWNTO 0); En : IN STD_LOGIC; y : OUT STD_LOGIC_VECTOR (3 downto 0)); END component; component dec4to16 IS PORT ( W : IN STD_LOGIC_VECTOR (3 DOWNTO 0); En : IN STD_LOGIC; y : OUT STD_LOGIC_VECTOR (15 downto 0)); END component; component trin IS GENERIC ( N : INTEGER : =8 ); PORT (X : IN STD_LOGIC_VECTOR ((N1) DOWNTO 0); E : IN STD_LOGIC; F : OUT STD_LOGIC_VECTOR ((N1) DOWNTO 0)); |library ieee; use ieee.std_logic_1164.a11; use work. components. a17; entity add_isa is port ( ock, reset : in std_logic; current_pc, result : out std__logic_vector (3 downto 0 )); end add_isa; architecture behaviour of add_isa is constant initial_pc : std_Togic_vector (3 downto 0 ) := (others ' 0 ') signal update_pc, read_port1, read_port2, write_port, w_value, src1, src2, sum, rout, mout : std_logic_vector(3 downto 0); signal instr_from_im istd_logic_vector (31 downto 0); signal MemRead, Memwrite, Regwrite, add_sub : std_logic; signal ALUOPE: std_logic_vector (1 downto 0); signal endresu7t: std_logic_vector (3 downto 0); signal ZERO2: std_logic; begin pc_mux : mux2to1 generic map (n=>4) port map (reset, update_pc, initia1_pc, mout); -- multiplexer pc : regn generic map ( n=>4 ) port map (clock, mout, rout); --- register addpc : ripple_carry port map (' 0%, rout, "0001", update_pc); im : instruction_memory port map (clock, reset, rout, instr_from_im) id : instruction_decode port map (instr_from_im, MemRead, Memwrite, Regwrite, add_sub, read_port1, read_port2, write_port, ALuope); rf : register_file port map (clock, reset, Regwrite, read_port1, read_port2, write_port, endresult, src1, src2); newalu: ALU port map(src1, src2, add_sub, ALUOPE, endresu7t, ZERO2); current_pc 4) port map (reset, update_pc, initia1_pc, mout); -- multiplexer pc : regn generic map ( n=>4 ) port map (clock, mout, rout); --- register addpc : ripple_carry port map (' 0%, rout, "0001", update_pc); im : instruction_memory port map (clock, reset, rout, instr_from_im) id : instruction_decode port map (instr_from_im, MemRead, Memwrite, Regwrite, add_sub, read_port1, read_port2, write_port, ALuope); rf : register_file port map (clock, reset, Regwrite, read_port1, read_port2, write_port, endresult, src1, src2); newalu: ALU port map(src1, src2, add_sub, ALUOPE, endresu7t, ZERO2); current_pc