Please give modified tcl file.

Original tcl file:

# Elaborate the FIFO design

elaborate fifo1

current_design fifo1

link

# write clock with the clock period of 1 and with duty cycle of 50%

create_clock -name "wclk" -period 1.0 -waveform {0.0 0.5} wclk

# read clock with the clock period of .5 and with duty cycle of 50%

create_clock -name "rclk" -period 0.50 -waveform {0.0 0.25} rclk

#set_wire_load_mode enclosed

#set_wire_load_model -name 8000

set_operating_conditions ss0p95v125c_2p25v

#compile map the sequential cell exactly as in the rtl

compile -exact_map

echo check_timing command

check_timing -include {no_driving_cell no_input_delay partial_input_delay unconstrained_endpoints }

echo report_qor command

report_qor

echo report_constraint command (PWR-6, PWR-414, PWR-415 Warnings are ok)

report_constraint -all_violators -verbose

Modify the FIFO1.tcl file in order to better constrain the design as described in the lectures. 1. Constrain each IO appropriately for delay/load/drive, 2. Constrain each clock fully for latency/transition/uncertainty, 3. Constrain the extra items for the design/area/power mentioned in the lectures. 4. Add a new clock for the one that is missing. welk2x and the related constraints