please help

Consider the VHDL below. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use IEEE.std_logic_unsigned. all; entity my_counter is generic (N: positive := 8); port RESET : in std_logic; - reset pin CLK in std_logic; -- clock input DIR in std_logic; -- count direction --Y is the counter output Y : out std_logic_vector((N-1) downto @):=(others='@')) end entity: architecture ctr of my_counter is begin process (CLK, DIR, RESET) is variable x : unsigned ((N-1) downto O) begin - (others -> '); if (CLK'event and CLK = '1') then if (RESET='') then X (others -> @'); if (CLK'event and CLK = '1') then if (RESET='') then X (others => '0'); Y