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please help I got stuck on this. i just need the screenshot of the design In this lab, you are going to design S-R latches

please help I got stuck on this.
i just need the screenshot of the design
image text in transcribed
In this lab, you are going to design S-R latches via Logical Design Tool using following methods: 1) NOR gates 2) NAND gates For each method (NOR gates and NAND gates): 1. Compute the truth table using your design. 2. Fill up the K-Map for Q. 3. Compute the simplified equation

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