Please help me with this Verilog Exercise question!
Consider the circuit below which adds the two 2-bit numbers AjAo and BiBo (the delay of each gate is written on it), a bubble at the input of a gate means that input is inverted: BO 3ns 00 B1 A1 2ns A1 B1 Ins B1 BO A1 2ns A1 BO 2ns 3ns 02 A1 B1 , B1 BO 2ns 2ns A1 B1 2ns 5ns 01 - AO BO A1- B1-01 3ns A1 B1 BO 3ns a. What is the critical path delay of each output of this circuit? b. Write three Verilog module for the three sub-circuits (i.e. one for Oo, another for 01, and another for O2) using gate-level modeling (i.e. a netlist) with each gate delay as in the diagram above (i.e. include the delays in the Verilog code). Then combine these 3 modules into a single module (using module instantiation). c. Write another module for the whole circuit using a single assign statement for each output (i.e. you will have a total of 3 assign statements). Do not forget to model the delay of each output. d. Write a test bench that tests and verify the operation of the two modules in B & C above for the following input combinations (put 20 ns delay between each consecutive inputs) and verify that your circuits work properly. Comment on any difference you observe between the two circuits and attach a snapshot of the simulation results. Values of A & B in decimal A1Ao BiBo_(Binary) 00 01 0,1 2,0 1,1 1,3 3,1 2,3 3,3 10 00 01 01 01 11 11 01 10 11 11 11 Expected Result (020100) 001 010 010 100 100 101 110 Consider the circuit below which adds the two 2-bit numbers AjAo and BiBo (the delay of each gate is written on it), a bubble at the input of a gate means that input is inverted: BO 3ns 00 B1 A1 2ns A1 B1 Ins B1 BO A1 2ns A1 BO 2ns 3ns 02 A1 B1 , B1 BO 2ns 2ns A1 B1 2ns 5ns 01 - AO BO A1- B1-01 3ns A1 B1 BO 3ns a. What is the critical path delay of each output of this circuit? b. Write three Verilog module for the three sub-circuits (i.e. one for Oo, another for 01, and another for O2) using gate-level modeling (i.e. a netlist) with each gate delay as in the diagram above (i.e. include the delays in the Verilog code). Then combine these 3 modules into a single module (using module instantiation). c. Write another module for the whole circuit using a single assign statement for each output (i.e. you will have a total of 3 assign statements). Do not forget to model the delay of each output. d. Write a test bench that tests and verify the operation of the two modules in B & C above for the following input combinations (put 20 ns delay between each consecutive inputs) and verify that your circuits work properly. Comment on any difference you observe between the two circuits and attach a snapshot of the simulation results. Values of A & B in decimal A1Ao BiBo_(Binary) 00 01 0,1 2,0 1,1 1,3 3,1 2,3 3,3 10 00 01 01 01 11 11 01 10 11 11 11 Expected Result (020100) 001 010 010 100 100 101 110
