Please help me with this VHDL Lab! I tried everything but I just cannot seem to understand what to write to get it to pass the tcl test. The professor said the the entity cannot be changed.

# Test HexTo7SegDecoder

# Procedure to run one test proc doTest {HEX exp_SEGMENT} {

# Apply input test values set_value -radix bin HEX $HEX

# Run simulation run 10ns

# Get output results set SEGMENT [get_value -radix bin SEGMENT] # Compare to expected results upvar numTests numTests incr numTests upvar numErrors numErrors # If test fails, print message with details if {$SEGMENT != $exp_SEGMENT} { incr numErrors puts "Error!! Inputs (HEX) = $HEX. Got SEGMENT = $SEGMENT, expected $exp_SEGMENT." } }

# Initialize simulation restart set numErrors 0 set numTests 0 puts " *********************************** Running tests..."

# Run tests by calling doTest with test inputs and expected outputs run 100ns

# doTest HEX exp_SEGMENT doTest 0000 0000001 doTest 0001 1001111 doTest 0010 0010010 doTest 0011 0000110 doTest 0100 1001100 doTest 0101 0100100 doTest 0110 0100000 doTest 0111 0001111 doTest 1000 0000000 doTest 1001 0001100 doTest 1010 0001000 doTest 1011 1100000 doTest 1100 0110001 doTest 1101 1000010 doTest 1110 0110000 doTest 1111 0111000

# Print summary of results puts "...done, found $numErrors error(s) in $numTests tests. ***********************************"

Here is the test map in case it's needed

library IEEE; IEEE. STD LOGIC 1164.ALL; entity HexTo7Seg Decoder is port ( HEX : in STD LOGIC VECTOR(3 downto 0); SEGMENT : out STD LOGIC VECTOR (0 to 6) end entity; architecture Structural of HexTo7Seg Decoder is begin SEGMENT