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Please help! Question 1 (8 pt.) The following diagram represents the single-cycle datapath studied in class with support for a subset of the MIPS arithmetic-logic

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Question 1 (8 pt.) The following diagram represents the single-cycle datapath studied in class with support for a subset of the MIPS arithmetic-logic instructions, plus 1w, sw, and beq. Control signals appear highlighted in blue. Branch RegWrite AluOp write PC in outaddress 25.21 MemWrite read_index1 read_index2 write_index write_data MemToReg read data1 op1 20..16 AluSrc zero write instr resu ess read data2 Adder4 out in Instruction memory read data Data 5.11 op2 ALU memory data RegDst Register file Shift left 15..0 in Sign extend out Adder result op2 MIPS instruction j (jump) performs an unconditional jump to a destination address. The instruction is encoded using the J format, where field imm (bits 25..0) represents bits 27..2 of the target address (see MIPS reference card). Bits 1..0 of the target address are always 0, since the address of an instruction in memory is always a multiple of 4. Finally, bits 31..28 of the target address are taken directly from the 4 most significant bits of the current program counter (PC register). Question 1 (8 pt.) The following diagram represents the single-cycle datapath studied in class with support for a subset of the MIPS arithmetic-logic instructions, plus 1w, sw, and beq. Control signals appear highlighted in blue. Branch RegWrite AluOp write PC in outaddress 25.21 MemWrite read_index1 read_index2 write_index write_data MemToReg read data1 op1 20..16 AluSrc zero write instr resu ess read data2 Adder4 out in Instruction memory read data Data 5.11 op2 ALU memory data RegDst Register file Shift left 15..0 in Sign extend out Adder result op2 MIPS instruction j (jump) performs an unconditional jump to a destination address. The instruction is encoded using the J format, where field imm (bits 25..0) represents bits 27..2 of the target address (see MIPS reference card). Bits 1..0 of the target address are always 0, since the address of an instruction in memory is always a multiple of 4. Finally, bits 31..28 of the target address are taken directly from the 4 most significant bits of the current program counter (PC register)

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