Please help thank you

Introduction

In this lab, you need to employ Always blocks, If statements, and For loops, as you

have learned in this lab session. The module should be implemented on this assignment is a

Priority Encoder.

Priority Encoder

A priority encoder is a module with $2$n inputs that maps to n outputs to represent input as

a binary code in output. You can look to this as one $2$n$-$bit input and one n$-$bit output. The

truth table of an encoder is as follows:

Figure $1$: Encoder Truth Table

As it can be seen in Figure $1,$ this output indicates that which input is $1,$ and the order is

important, i$.$e$.,$ when D$0=1$ and D$1=1$ simultaneously $($ D $=0011),$ D$0=1$ will be

considered. The valid bit is $0,$ only when D $=0000($all the bits of input is $0).$ Figure $2$

illustrates the inputs and outputs of a module with $4$ inputs and $2$ outputs as an example.

Assignment Description

Design a Verilog module that implements a $32-$to$-5$ priority encoder. The encoder will

take one $32-$bit input and output one $5-$bit binary code representing the highest priority input

that is active $($logic $1).$ Inputs have a priority such that the least significant bit $($LSB$)$ has the

highest priority, and the most significant bit $($MSB$)$ has the lowest priority. In other words, for

example, when D$0,1,2,3,4,5=0,$ but D$6=1,$ the value of other left bits $($ D$7,$ D$8,$

$...,$ D$31)$ is not important, and output should be $6$ in a $5$b$-$bit binary, i$.$e$.,$ Y $=00110.$

$1$

Lab $3$ Structural VLSI Design

Figure $2$: $47->2$ Encoder Inputs and Outputs

Ports

The module should have the following inputs and outputs:

$$ D : INPUT. A single $32-$bit input where each bit represents a different input signal. Only

one input will be active at a time.

$$ Y : OUTPUT. A single $5-$bit output representing the binary code of the highest priority

input that is active.

$$ valid : OUTPUT. A $1-$bit output that is high $(1)$ if any input is active $($i$.$e$.,$ at least one

bit of A is $1),$ and low $(0)$ otherwise.

Test Cases of the Simulation

$1.$ D $=32$h$80000000->$ Y $=5$b$11111$ and valid $=1.$

$2.$ D $=32$h$00000008->$ Y $=5$b$00011$ and valid $=1.$

$3.$ D $=32$h$00400000->$ Y $=5$b$10110$ and valid $=1.$

$4.$ D $=32$h$00000400->$ Y $=5$b$01010$ and valid $=1.$

$5.$ D $=32$h$00020000->$ Y $=5$b$10001$ and valid $=1.$

$6.$ D $=32$h$11218000->$ Y $=5$b$01111$ and valid $=1.$

$7.$ D $=32$h$42022100->$ Y $=5$b$01000$ and valid $=1.$

$8.$ D $=32$h$00000001->$ Y $=5$b$00000$ and valid $=1.$

$9.$ D $=32$h$00000000->$ Y $=5$b$00000$ and valid $=0.$

$2$

Lab $3$ Structural VLSI Design

What to Submit

For the labs, you have to prepare just a single PDF file as your lab report. The lab report

should contain these materials:

$1.$ The waveform of the output. Take a screenshot from the waveform, and put it in the

waveform section of the report. $(20\%)$

$2.$ The schematic of the design. Take a screenshot from the schematic, and put it in the

schematic section of the report. $(20\%)$

$3.$ Your Verilog code of the design. Copy all the lines of your design code to your report

in a Microsoft Word document, or if you are using LATEX, you can use the listings

package to put your code in a document, which is the recommended way. $(30\%)$

$4.$ Your Verilog code of the testbench. Copy all the lines of your testbench code to

your report in a Microsoft Word document, or if you are using LATEX, you can use the

listings package to put your code in a document, which is the recommended way.

$(30\%)$

Final Notes

$$ You must utilize a behavioral design. No other design, like gate$-$level or data flow is

acceptable, and will get a ZERO grade. You should use For loops and if statements,

all in an Always block.

$$ You can only upload a PDF file. If you are using Microsoft Word, convert it to a PDF file

and upload it$.$ If you are using LATEX for the assignments, just upload the generated PDF

file.

$$ Writing any other information on the lab report is not mandatory. You can put only those

four sections in your lab report, or you can add some additional information on your file.

It$$s up to yourselves, and no grades would have been assigned to additional information

and explanation.

$$ The waveform SHOULD be as clear as it can be$.$ The waveforms of the assignments that

don$$t comply with the "Beautifying Waveform" section in the lab $0,$ will result to losing

the points of the waveform part.

$$ Don$$t forget to set your testbench as Top Module before the simulation, or you will get

X $$s at the output, and you will lose the points of the waveform part.

Hint: If your Verilog testbench file in the Simulation Sources part of the Vivado, Sources,

is not boldface, right$-$click on it and select Set as Top $.$ If this option is disabled

$($grayed out$),$ it means that your file has already been set as a top simulation source.