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Two main techniques are used for memory management in modern computers and operating systems, as described in this module's readings: paging and segmentation. Sometimes they are combined in a segmentation with paging scheme. Design a memory management scheme for a 50 bit computer architecture, using paging, segmentation or both, as described in this module's readings. Your post should include a clear translation scheme from a 50 bit logical address to a 50 bit physical address including a picture that shows how this translation takes place. In particular, each field of the logical address must be clearly depicted and its length in bits must be specified. The proposed scheme must be at least somewhat realistic; for this reason, simple paging and simple segmentation schemes are automatically disqualified, due to the impossible requirements imposed on the implementation in this case ( 50 bits addresses). Your proposed scheme must be different from your colleagues' schemes. If you use the same general technique (say, segmentation with paging) your scheme must be different with regard to the details, like: fields of the logical address, their size, type of paging, etc