Please help with this coding project I need it to be in C or C++ thanks will give extra points and leave a thumbs up and a positive review.
Project Details Please read the following details carefully and follow them, when implementing your simulator: 1. Input trace: The simulator will take an address trace as its input. This trace captures the sequence of accesses that are being made to the cache. For each access, the trace provides the type of access and the memory address that is being accessed. Each line in the trace has the following format: Access_type Hex_Address Access_type signifies the type of the memory operation (read, write or invalidate). It is encoded as follows: Access_type = 0 indicates a read, Access_type = 1 indicates a write and Access_type = 2 indicates an invalidate operation. Hex_address is the address which is being accessed. It is encoded in the hexadecimal format. Each address is a 32-bit number (8 hexadecimal digits) and signifies the byte which is being accessed. The two fields in each line are separated by a whitespace. Example 1: Let us assume that the first line in the address trace is as follows: 0 00A53C00 This represents a read request to the byte address 0x00A53C00 Example 2: Consider another line in the address trace: 1 3044DB20 This represents a write request to the byte address 0x3C44DB20 Example 3: Another line in the address trace is as follows: 2 00A53C04 This represents an invalidation request for address Ox00A53C04. If the cache line that contains address 00A53C04 is present in the cache, then it should be evicted from the cache and its valid bit should be reset to 0. If the invalidated address is not present in the cache, then nothing needs to be done. 2. Cache Parameters: Your model should support the following parameters to be configurable: num_sets num_ways (associativity) line_size (in bytes) replacement_policy To simplify the implementation, you should assume that num_sets, num_ways and line_size are always powers of 2, maximum value of num_ways is 8 and line_size ranges from 32 to 128. The modeled cache should support the following two replacement policies: (i) True LRU (replacement_policy = 0), and (ii) 1-bit LRU (replacement policy = 1). When a new cache line is brought into a set, it should first look to occupy an invalid cache block in that set. If there is no invalid block, then the replacement policy should choose the appropriate block as victim to make room for the new line. The details of the true LRU and 1-bit LRU replacement policies were discussed in class and are included in the lecture slides (ece585_lec 10.pdf) As far as writes are concerned, you should assume a write-back cache with a write-allocate policy. You don't need to implement any timing details (such as hit time, miss penalty etc.) for the cache. 3. Simulator output: After the last access in the trace has been simulated, the simulator output should include the following statistics: Total number of cache accesses Number of cache reads Number of cache writes Number of invalidates Number of cache hits Number of cache misses Cache hit ratio Cache miss ratio Number of evictions Number of writebacks Project Details Please read the following details carefully and follow them, when implementing your simulator: 1. Input trace: The simulator will take an address trace as its input. This trace captures the sequence of accesses that are being made to the cache. For each access, the trace provides the type of access and the memory address that is being accessed. Each line in the trace has the following format: Access_type Hex_Address Access_type signifies the type of the memory operation (read, write or invalidate). It is encoded as follows: Access_type = 0 indicates a read, Access_type = 1 indicates a write and Access_type = 2 indicates an invalidate operation. Hex_address is the address which is being accessed. It is encoded in the hexadecimal format. Each address is a 32-bit number (8 hexadecimal digits) and signifies the byte which is being accessed. The two fields in each line are separated by a whitespace. Example 1: Let us assume that the first line in the address trace is as follows: 0 00A53C00 This represents a read request to the byte address 0x00A53C00 Example 2: Consider another line in the address trace: 1 3044DB20 This represents a write request to the byte address 0x3C44DB20 Example 3: Another line in the address trace is as follows: 2 00A53C04 This represents an invalidation request for address Ox00A53C04. If the cache line that contains address 00A53C04 is present in the cache, then it should be evicted from the cache and its valid bit should be reset to 0. If the invalidated address is not present in the cache, then nothing needs to be done. 2. Cache Parameters: Your model should support the following parameters to be configurable: num_sets num_ways (associativity) line_size (in bytes) replacement_policy To simplify the implementation, you should assume that num_sets, num_ways and line_size are always powers of 2, maximum value of num_ways is 8 and line_size ranges from 32 to 128. The modeled cache should support the following two replacement policies: (i) True LRU (replacement_policy = 0), and (ii) 1-bit LRU (replacement policy = 1). When a new cache line is brought into a set, it should first look to occupy an invalid cache block in that set. If there is no invalid block, then the replacement policy should choose the appropriate block as victim to make room for the new line. The details of the true LRU and 1-bit LRU replacement policies were discussed in class and are included in the lecture slides (ece585_lec 10.pdf) As far as writes are concerned, you should assume a write-back cache with a write-allocate policy. You don't need to implement any timing details (such as hit time, miss penalty etc.) for the cache. 3. Simulator output: After the last access in the trace has been simulated, the simulator output should include the following statistics: Total number of cache accesses Number of cache reads Number of cache writes Number of invalidates Number of cache hits Number of cache misses Cache hit ratio Cache miss ratio Number of evictions Number of writebacks
