Please help with this problem.

Instructions:

Add new rows for Shift Left Logical, Shift Right Logical, Shift Right Arithmetic

32 bit single cycle MIPS processor Fill in the truth table for these three instructions disregard the ALUcnt column

format R 1 Name Add Addi and andi Beq Lw Nor Or Sit SII ALUop 10 00 10 11 01 00 10 10 Instruction[31:26) Instruction[5:0) 000000 100000 001000 000000 100100 001100 000100 100011 000000 100111 000000 100101 000000 101010 110000 000000 110000 000010 110000 000011 101011 000000 100010 000000 100110 000000 011000 000000 011010 000010 R I 1 1 R R R R R R 1 R R R R j alu control 0010 0010 0000 0000 0110 0010 1100 0001 0111 1000 1001 1010 0010 0110 0100 0101 1011 Srl sra Sw Sub xor Mult div jump 10 10 10 10 00 10 10 10 10 Control unit design: Control signals Instruction Memto Reg MemRead Mem Branch ALUOP Jump Reg ALU Dst Src Reg Write Write R-type 1 0 0 1 0 0 0 00 0 LW 0 1 1 1 1 0 0 11 0 SW 0 1 0 0 0 1 0 11 0 addi 0 1 0 1 0 0 0 11 0 beq 0 0 0 0 0 0 1 01 0 j 0 0 0 0 0 0 0 00 1 jal 2 0 2 1 0 0 0 00 1 slti 0 1 0 1 0 0 0 10 0 format R 1 Name Add Addi and andi Beq Lw Nor Or Sit SII ALUop 10 00 10 11 01 00 10 10 Instruction[31:26) Instruction[5:0) 000000 100000 001000 000000 100100 001100 000100 100011 000000 100111 000000 100101 000000 101010 110000 000000 110000 000010 110000 000011 101011 000000 100010 000000 100110 000000 011000 000000 011010 000010 R I 1 1 R R R R R R 1 R R R R j alu control 0010 0010 0000 0000 0110 0010 1100 0001 0111 1000 1001 1010 0010 0110 0100 0101 1011 Srl sra Sw Sub xor Mult div jump 10 10 10 10 00 10 10 10 10 Control unit design: Control signals Instruction Memto Reg MemRead Mem Branch ALUOP Jump Reg ALU Dst Src Reg Write Write R-type 1 0 0 1 0 0 0 00 0 LW 0 1 1 1 1 0 0 11 0 SW 0 1 0 0 0 1 0 11 0 addi 0 1 0 1 0 0 0 11 0 beq 0 0 0 0 0 0 1 01 0 j 0 0 0 0 0 0 0 00 1 jal 2 0 2 1 0 0 0 00 1 slti 0 1 0 1 0 0 0 10 0