please include number 3 completed diagram and number 4 test bench. -xiling ise simulation and vhdl test bench.

thank you

3. We need to keep the value from the output of the adder in a register. Since the adder is 8- bit wide, we will need to have an 8-bit register. In this lab, we wil use FD8RE from the library, a Macro: 8-Bit Data Register with Clock Enable and Synchronous Reset. This design element is an 8-bit data register. When the clock enable (CE) input is High, and the synchronous reset (R) input is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q) during the Low-to-High clock (C) transition (rising edge) When R is High, it overrides all other inputs and resets the data outputs (Q) Low on the Low-to-High clock transition. When CE is Low, clock transitions are ignored. D[70] Q[7:0] CE FD8RE Add FD8RE to your design. You will connect the output Q to the port A of the adder, and the port D to the output port S of the adder. Additionally, you will need I/O markers for CE, C, and R. So you may set values in your test bench later. When done, synthesize your design, and show your design in ISE check 4. Create a test bench named "counter tb" for your design. Add stimuli test cases. The first one should be reset, followed by test cases that increases the counter from 0, 1, 2, 3, 4, .., 255, 0, 1,2.. Place assert statements accordingly. You test cases should include at least 3 scenarios: initialization, increment, and fallback (255 to 0). Because the counter changes its value on a rising edge of the clock, you will need to simulate the rising edge in your stimuli design. Below is a sample code: -- test 1: reset -- reset - clock enable -- set clock low --specify half period of clock -- set clock high -- specify another half period wait for 10 ns; wait for 10 ns; assert Q "00000000" report "test 1 failed"; You may design a second test to check if the counter increases its value to 1 after two rising edges. However, to design a test case for the fallback case is a challenge. You may add 255 rising edges followed by the test case for the fallback scenario. It is doable but awkward. To check the fallback case, remove test 1 (initialization), any wait statements after test 2, and any assert statements (why). Then you should be able to check the fallback case in the waveform. For some of you really curious on using assert statement for the fallback case, you may add a cycle counter as an integer signal, and increase its value by one in the test process. You then should be able to assert Q along with the cycle counter (10% extra credits). Run the simulation and check the simulation wave forms, and console outputs to verify the correctness of the circuit check 3. We need to keep the value from the output of the adder in a register. Since the adder is 8- bit wide, we will need to have an 8-bit register. In this lab, we wil use FD8RE from the library, a Macro: 8-Bit Data Register with Clock Enable and Synchronous Reset. This design element is an 8-bit data register. When the clock enable (CE) input is High, and the synchronous reset (R) input is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q) during the Low-to-High clock (C) transition (rising edge) When R is High, it overrides all other inputs and resets the data outputs (Q) Low on the Low-to-High clock transition. When CE is Low, clock transitions are ignored. D[70] Q[7:0] CE FD8RE Add FD8RE to your design. You will connect the output Q to the port A of the adder, and the port D to the output port S of the adder. Additionally, you will need I/O markers for CE, C, and R. So you may set values in your test bench later. When done, synthesize your design, and show your design in ISE check 4. Create a test bench named "counter tb" for your design. Add stimuli test cases. The first one should be reset, followed by test cases that increases the counter from 0, 1, 2, 3, 4, .., 255, 0, 1,2.. Place assert statements accordingly. You test cases should include at least 3 scenarios: initialization, increment, and fallback (255 to 0). Because the counter changes its value on a rising edge of the clock, you will need to simulate the rising edge in your stimuli design. Below is a sample code: -- test 1: reset -- reset - clock enable -- set clock low --specify half period of clock -- set clock high -- specify another half period wait for 10 ns; wait for 10 ns; assert Q "00000000" report "test 1 failed"; You may design a second test to check if the counter increases its value to 1 after two rising edges. However, to design a test case for the fallback case is a challenge. You may add 255 rising edges followed by the test case for the fallback scenario. It is doable but awkward. To check the fallback case, remove test 1 (initialization), any wait statements after test 2, and any assert statements (why). Then you should be able to check the fallback case in the waveform. For some of you really curious on using assert statement for the fallback case, you may add a cycle counter as an integer signal, and increase its value by one in the test process. You then should be able to assert Q along with the cycle counter (10% extra credits). Run the simulation and check the simulation wave forms, and console outputs to verify the correctness of the circuit check