Please provide the answers for both parts of the questions. Need ASAP

ANSWER please

Consider a latch comprised of NOR rather than NAND gates: Homework 1 A. Storage 1 point possible (graded) For inputs R = 1 and 5 = 0, which of the following is true? Q = 0 and = 0 Q = 0 and 7 = 1 Q = 1 and = 1 Q = 1 and @ = 0 Which input combination will retain the outputs from part A? [Check all that apply] R = 0 and 5 = 0. R = 0 and 5 = 1. R= 1 and 5 = 0. A 2-bit loadable register uses two D flip-flops with load capability that share one LD input and one clock input. If currently D, D = 01, LD = 0, and Q- Qo = 10, what will be the new value of Q, Qo when the clock triggers (transitions from 0 to 1)? 00 O 01 010 11