please use Quartzsite software to design a two magnitude comparator. also show the waves of each design. show where I can place the renaming. thanks for the help.

Part 1 Now you are ready to design a two-bit magnitude comparator using two one-bit comparators and "glue" gates. (50 points) You will need three block diagrams, one for the top hardware level Altera Board implementation, one for the structural two-bits magnitude comparator, and one for the one-bit magnitude comparator. a. Draw a block diagram for a two-bits magnitude comparator that uses instances of your one- bit magnitude comparator and any other logic gates needed b. Do the simulation and save the waves to your report. Aw-bit-comp-top c. Rename your ports and download your two-bits comparator to your FPGA board. Hardware Signals SW[3:2] SW[1:0) LEDR(2:0) LEDR[6:3] Magnitude Comparator A[1:0] B[1:0) LT, GT, EQ SW[3:0] show switch states on red LEDS Import pin assignments. Compile and then burn/download the program to the Altera board. d. Please take photos to your board in the following cases: Output LT 0 A1 0 0 1 Input Binary Values 0 B1 1 0 1 0 0 1 0 0 1 1 GT 1 0 0 EQ 0 1 0 0 1