Please use the EDAplayground to finish this program, and the code is available in this website: https://www.edaplayground.com/x/3aGb

Part 1: The ALU The ALU is a relatively straightforward construction in Verilog, if you make use of operators available to Verilog. The ALU has three main components: A register called A, which stores the first operand. A connection to the bus, which will contain the second operand, and a register C, to output the result. Between all of these components is a combinational circuit which will perform the desired operations. Note that in the following diagram, the star (*) represents a logical subsection of the module, and not another actual module. cpu bus A uA out Note: There are two slight differences between the above circuit and the ALU for the SRC discussed in the lectures. Firstly, the above circuit does not include the a_out line. It is assumed that the data in the register is automatically available to the arithmetic processing section. Secondly, the shc control line is not implemented since Verilog does not support it as a default operator. The important part here is how the control logic is performed so that the CPU can make use of it. There are three distinct steps to performing an operation on the ALU (these may vary for certain operations): 1. A value is loaded into register A using the bus, and the a_in input. Once a_in is set to 1, A should Part 1: The ALU The ALU is a relatively straightforward construction in Verilog, if you make use of operators available to Verilog. The ALU has three main components: A register called A, which stores the first operand. A connection to the bus, which will contain the second operand, and a register C, to output the result. Between all of these components is a combinational circuit which will perform the desired operations. Note that in the following diagram, the star (*) represents a logical subsection of the module, and not another actual module. cpu bus A uA out Note: There are two slight differences between the above circuit and the ALU for the SRC discussed in the lectures. Firstly, the above circuit does not include the a_out line. It is assumed that the data in the register is automatically available to the arithmetic processing section. Secondly, the shc control line is not implemented since Verilog does not support it as a default operator. The important part here is how the control logic is performed so that the CPU can make use of it. There are three distinct steps to performing an operation on the ALU (these may vary for certain operations): 1. A value is loaded into register A using the bus, and the a_in input. Once a_in is set to 1, A should